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MIL-STD-750D, Test Methods for Semiconductor …

MIL-STD-750D Test Methods for Semiconductor Devices. MIL-STD-750D 1. This Military Standard is approved for use by all Departments and Agencies of the Department of ...

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Text of MIL-STD-750D, Test Methods for Semiconductor …

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Broad Street,Columbus, OH 45316 by using the Standardization Document Improvement Proposal (DD Form 1426) appearing at the end ofthis document or by Entire standard Page Paragraph Numbering Classification of Method of Government Specifications, standards, and Other Government documents, drawings, and Non-Government Order of Abbreviations, symbols, and Abbreviations used in this standard .......................................................................................... Test Permissible temperature variation in environmental Electrical test Test methods and Calibration General Test conditions for electrical Pulse Test Test method Order of connection of Radiation Handling precautions ................................................................................................................ UHF and microwave devices .................................................................................................... Electrostatic discharge sensitive (ESDS) devices .................................................................... Continuity verification of burn-in and life tests .......................................................................... Bias Requirements for HTRB and burn-in ........................................................................................ Bias requirements .................................................................................................................... REQUIREMENTS .................................................................................................... International standardization 12FIGURES of noncylindrical semiconductor device to directionof accelerating force .................................................................................................................. of cylindrical semiconductor device to directionof accelerating 7INDEX IndexNumerical index of test 15iiMIL-STD-750D1. Purpose. This standard establishes uniform methods for testing semiconductor devices, including basic environmentaltests to determine resistance to deleterious effects of natural elements and conditions surrounding military operations, andphysical and electrical tests. For the purpose of this standard, the term "devices" includes such items as transistors, diodes,voltage regulators, rectifiers, tunnel diodes, and other related parts. This standard is intended to apply only to semiconductordevices. The test methods described herein have been prepared to serve several specify suitable conditions obtainable in the laboratory that give test results equivalent to the actual serviceconditions existing in the field, and to obtain reproducibility of the results of tests. The tests described herein are notto be interpreted as an exact and conclusive representation of actual service operation in any one geographic location,since it is known that the only true test for operation in a specific location is an actual service test at that describe in one standard all of the test methods of a similar character which now appear in the variousjoint-services semiconductor device specifications, so that these methods may be kept uniform and thus result inconservation of equipment, manhours, and testing facilities. In achieving this objective, it is necessary to make eachof the general tests adaptable to a broad range of test methods described herein for environmental, physical, and electrical testing of devices shall also apply, whenapplicable, to parts not covered by an approved military sheet-form standard, specification sheet, or Numbering system. The test methods are designated by numbers assigned in accordance with the following Classification of tests. The tests are divided into five areas. Test methods numbered 1001 to 1999 inclusive, coverenvironmental tests; those numbered 2001 to 2999 inclusive cover mechanical- characteristics tests. Electrical- characteristicstests are covered in two groups; 3001 to 3999 inclusive covers tests for transistors and 4001 to 4999 covers tests for methods numbered 5000 to 5999 inclusive are for high reliability space Revisions. Revisions are numbered consecutively using a period to separate the test method number and the revisionnumber. For example, is the first revision of test method Method of reference. When applicable, test methods contained herein shall be referenced in the individual specification byspecifying this standard, the method number, and the details required in the summary of the applicable method. To avoid thenecessity for changing specifications that refer to this standard, the revision number should not be used when referencing testmethods. For example, use 4001, not APPLICABLE General. The documents listed in this section are specified in sections 3 and 4 of this standard. This section does notinclude documents cited in other sections of this standard or recommended for additional information or as examples. Whileevery effort has been made to ensure the completeness of this list, document users are cautioned that they must meet allspecified requirements documents cited in sections 3 and 4 of this specification, whether or not they are Government Specifications, standards, and handbooks. The following specifications, standards, and handbooks form a part of thisdocument to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issueof the Department of Defense Index of Specifications and Standards (DODISS) and supplement thereto, cited in the solicitation(see ).SPECIFICATIONSMILITARYMIL-S-19500 - Semiconductor Devices, General Specification for used on Drawings, Specification Standards & in TechnicalDocumentsMIL-STD-202-Test Methods for Electronic and Electrical Component Systems -Electrostatic Discharge Control Program for Protection of Electrical andElectronic Parts, Assemblies and Equipment (Excluding Electrically InitiatedExplosive Devices) (Metric).HANDBOOKSMILITARYMIL-HDBK-263-Electrostatic Discharge Control Handbook for Protection of Electrical andElectronic Parts, Assemblies and Equipment (Excluding Electrically InitiatedExplosive Devices) (Metric).(Unless otherwise indicated, copies of federal and military specifications, standards, and handbooks are available from theStandardization Document Order Desk, 700 Robbins Avenue, Bldg. 4D, Philadelphia, PA 19111-5094.) Other Government documents, drawings, and publications. The following other Government documents, drawings, andpublications form a part of this document to the extent specified herein. Unless otherwise specified, the issues are those cited inthe - JAN103-JAN-Filter for Testing Crystal Rectifier 1N23, 1N23A and for Testing Crystal Rectifier Type of Merit Holder for Crystal Rectifier and Coupling Circuit for Crystal Rectifiers Band Crystal Detector Test for Electron Tube Type Out Testing Equipment for 1N25 Crystals Schematic Measuring Equipment for 1N25 Crystals Schematic Measuring Equipment for 1N25 Crystals Bill of Out Testing Equipment for 1N25 Crystals Bill of Pulse Recovery Time Test and Calibration Holder, Narrow, Band, for - DESC ASSEMBLYD64100-Diode Test Holder, 3,060 MHz (S-Band).C64169-Sliding Load (S-Band) Used with , Tri-polar Diode Test Holder, 9,375 GHz (X-Band).C65042-Sliding Load (X-Band) Used with Test Holder, 16 GHz (Ku-Band).C65101-Sliding Load (Ku-Band) Used with Holder, Narrow Band, for -Adaptor For Burn-Out Tester For Microwave (Copies of drawings may be obtained from the Defense Supply Center Columbus, (DSCC-VAT), 3990 E. Broad Street,Columbus, Ohio 45316. When requesting copies of these drawings, both the identifying symbol number and title should bestipulated.) Non-Government publications. The following documents form a part of this document to the extent specified otherwise specified, the issues of the documents which are DoD adopted are those listed in the DODISS cited in thesolicitation. Unless otherwise specified, the issues of documents not listed in the DODISS are the issues of the documents citedin the solicitation (see ).Standard Handbook for Electrical Engineers.(Application for copies should be addressed to the McGraw-Hill Book Company, Inc., New York, 42840.)NBS Handbook 59 - Permissible Dose From External Sources of Ionizing Radiation, Recommendations of National Committee on Radiation Handbook 73 - Protection Against Radiations from Sealed Gamma Handbook 76 - Medical X-Ray Protection Up to 3 Million Volts.(Application for copies should be addressed to the Superintendent of Documents, Washington, DC 20402.) Order of precedence. In the event of a conflict between the text of this document and the references cited herein, the textof this document takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless aspecific exemption has been Abbreviations, symbols, and definitions. For the purposes of this standard, the abbreviations, symbols, and definitionsspecified in MIL-S-19500, MIL-STD-12, and herein shall Abbreviations used in this standard. Abbreviations used in this standard are defined as follows: test equipment. instability shock test. physical analysis. under test. discharge. discharge sensitivity. transistor. instability shock test. half-max. temperature reverse bias. frequency. gate bipolar transistor. chip carrier. accelerator. oxide semiconductor field-effect transistor. impact noise detection. q. RH-Relative humidity. electron microscope. operating area. operating power. test unit. wave ratio. dosimetry. sensitive GENERAL Test conditions. Unless otherwise specified herein or in the individual specification, all measurements and tests shall bemade at thermal equilibrium at an ambient temperature of 25qC r3qC and at ambient atmospheric pressure and relative humidityand the specified test condition C (at environmentally elevated and reduced temperatures) shall have a tolerance of 3 percent or+3qC, whichever is greater. Whenever these conditions must be closely controlled in order to obtain reproducible results, thereferee conditions shall be as follows: temperature 25qC 1qC, relative humidity 50 5 percent, and atmospheric pressure from650 to 800 millimeters of mercury. Unless otherwise specified in the detail test method, for mechanical test methods, 2000series, the ambient temperature may be 25qC Permissible temperature variation in environmental chambers. When chambers are used, specimens under test shallbe located only within the working area defined as variation within working area: The controls for the chamber shall be capable of maintaining thetemperature of any single reference point within the working area within 2qC or 4 percent, whichever is variation within working area: Chambers shall be so constructed that, at any given time, the temperature of anypoint within the working area shall not deviate more than 3qC or 3 percent, whichever is greater, from the referencepoint, except for the immediate vicinity of specimens generating with specified minimum temperatures (such as those used in burn-in and life tests): When testrequirements involve a specified minimum test temperature, the controls and chamber construction shall be such thatthe temperature of any point within the working area shall not deviate more than +8qC, -0qC; or +8 percent, -0 percent,whichever is greater, from the specified minimum temperature, except for the immediate vicinity of the specimensgenerating Electrical test frequency. Unless otherwise specified, the electrical test frequency shall be 1,000 25 Hertz (Hz). Accuracy. The specified limits are for absolute (true) values, obtained with the specified (nominal) test allowance shall be made for measurement errors (including those due to deviations from nominal test conditions) inestablishing the working limits to be used for the measured values, so that the true values of the device parameters (as theywould be under nominal test conditions) are within the specified following electrical test tolerances and precautions, unless otherwise specified in the applicable acquisition document, shallbe maintained for all device measurements to which they apply (3000, 4000 series and other specified electrical measurements).Wherever test conditions are specified in the applicable acquisition document to a precision tighter than the tolerances indicatedbelow, the specified conditions shall apply and take precedence over these general conditions shall be held to within 3 percent of the specified properties as input pulse characteristics, repetition rates, and frequencies shall be held to within 10 values should be chosen so that 10 percent variation (or the actual test equipment variation, if less than 10percent) does not affect the accuracy or validity of the measurement of the specified applied in breakdown testing shall be held within 1 percent of specified loads shall be 5 percent loads shall be 10 percent or 1 picofarad (pF) tolerance, whichever is loads shall be 10 percent or 5 microhenries (mH) tolerance, whichever is parameters shall be measured to within 1 parameters shall be measured to within 5 percent or 1 nanosecond (ns), whichever is Test methods and circuits. Unless otherwise stated in the specific test method, the methods and circuits shown aregiven as the basic measurement method. They are not necessarily the only method or circuit which can be used, but themanufacturer shall demonstrate to the acquiring activity that alternate methods or circuits which he may desire to use areequivalent and give results within the desired accuracy of measurement (see ). Calibration requirements. Calibration and certification procedures shall be provided in accordance with MIL-STD-45662for plant standards and instruments used to measure or control production processes and semiconductor devices under those measurements that are not traceable to the National Institute of Standards and Technology (NIST), correlation samplesshall be maintained and used as the basis of proving acceptability when such proof is required. In addition, the followingrequirements shall accuracy of a calibrating instrument shall be at least four times greater than that of the item being calibrated,unless the item being calibrated is state of the art equipment, which may be near or equal in accuracy to the state ofthe art calibrating equipment, in which case the four time requirement does not apply. However, the instrument shallbe calibrated to correlate with standards established by the in those cases where the NIST recommends a longer period and concurrence is obtained from the qualifyingactivity, calibration intervals for plant electrical standards shall not exceed one year, and for plant mechanical standardsshall not exceed two Orientations:X is the orientation of a device with the main axis of the device normal to the direction of the accelerating force, and themajor cross section parallel to the direction of the accelerating is the orientation of a device with the main axis of the device parallel to the direction of the accelerating force, and theprincipal base toward (Y1), or away from (Y2), the point of application of the accelerating is the orientation of a device with the main axis and the major cross section of the device normal to the direction of theaccelerating force. Z is 90q of X. NOTE: For case configurations, other than those shown on figures 1 and 2, the orientation of the device shall be as specified in the individual 1. Orientation of noncylindrical semiconductor device to direction of accelerating 2. Orientation of cylindrical semiconductor device to direction of accelerating General precautions. The following precautions shall be observed in testing the Transients. Devices shall not be subjected to conditions in which transients cause the rating to be Test conditions for electrical measurements. Unless otherwise required for a specified test method, semiconductordevices should not be subjected to any condition that will cause any maximum rating of the device to be exceeded. Theprecautions should include limits on maximum instantaneous currents and applied voltages. High series resistances (constantcurrent supplies) and low capacitances are usually required. If low cutoff, or reverse current devices are to be measured, forexample, nanoampere units, care should be taken to ensure that parasitic circuit currents or external leakage currents are small,compared with the cutoff or reverse current of the device to be Steady state dc measurements (method 4000). Unless otherwise specified, all steady state dc parameters are definedusing steady state dc Pulse measurements (method 4000). When device static or dynamic parameters are measured under "pulsed"conditions, in order to avoid measurement errors introduced by device heating during the measurement period, the followingitems should be covered in the detail statement "Pulsed test" shall be placed by the test otherwise specified, the pulse time (tp) shall be d10 milliseconds and the duty cycle shall be a maximum of 2percent; within this limit the pulse must be long enough to be compatible with test equipment capability and theaccuracy required, and short enough to avoid Test circuits. The circuits shown are given as examples which may be used for the measurements. They are notnecessarily the only circuits which can be used but the manufacturer shall demonstrate to the Government that other circuitswhich he may desire to use will give results within the desired accuracy of measurement. Circuits are shown for PNP transistorsin one circuit configuration only. They may readily be adapted for NPN devices and for other circuit Test method variation. Variation from the specified test methods used to verify the electrical parameters are allowedprovided that it is demonstrated to the preparing activity or their agent that such variations in no way relax the requirements ofthis specification and that they are approved before testing is performed. For proposed test variations, a test methodcomparative error analysis shall be made available for checking by the preparing activity or their Soldering. Adequate precautions shall be taken to avoid damage to the device during soldering required for Order of connection of leads. Care should be taken when connecting a semiconductor device to a power source. Thecommon terminal shall be connected Radiation precautions. Due precautions shall be used in storing or testing semiconductor devices in substantial fields ofX-rays, neutrons, or other energy Handling UHF and microwave devices. Handling precautions for UHF and microwave devices shall be as all hand contact to the equipment while holding the base end and maintain hand contact with the equipment untilthe device is in applicable, keep devices in metal shields until they are inserted in the equipment or until necessary to removefor Electrostatic discharge sensitive devices. Handling precautions shall be observed in accordance withDOD-HDBK-263 during testing of Electrostatic Discharge Sensitive (ESDS) devices. The area where ESDS device tests areperformed shall meet the requirements of an ESD Protected Area of Continuity verification of burn-in and life tests. The test setup shall be monitored at the test temperature initially and at theconclusion of the test to establish that all devices are being stressed to the specified requirements. The following is the minimumacceptable monitoring sockets. Initially and at least each 6 months thereafter, each test board or tray shall be checked to verifycontinuity to connector points to assure that the correct voltage bias will be applied. Except for this initial and periodicverification, each device or device socket does not have to be checked; however, random sampling techniques shallbe applied prior to each time a board is used and shall be adequate to assure that there are correct and continuouselectrical connections to the to test boards or trays. After the test boards are loaded with devices, inserted into the system, andbrought up to the specified operating conditions, each required test voltage and signal condition shall be verified in atleast one location on each test board or tray so as to assure electrical continuity and the correct application ofspecified electrical stresses for each connection or contact pair used in the applicable test configuration. The systemmay be opened for a maximum of 10 the conclusion of the test period, prior to removal of devices from temperature and bias conditions, the voltage andsignal condition verification of shall be class S devices, each test board or tray and each test socket shall be verified prior to test to assure that thespecified bias conditions are applied to each device. This may be accomplished by verifying the device functionalresponse at each device output(s) or by performing a socket verification on each socket prior to loading. An approvedalternate procedure may be Bias interruption. Where failures or open contacts occur which result in removal of the required bias stresses for anyperiod of the required bias duration, the bias time shall be extended to assure actual exposure for the total minimum specified testduration. Any loss(es) or interruption(s) of bias in excess of 10 minutes total duration while the chamber is at temperature duringthe final 8 hours of burn-in shall require extension of the bias duration for an uninterrupted 8 hours minimum, after the last Requirements for HTRB and temperature of +20qC minimum is the ambient air temperature to which all devices should be exposed duringpower screening where room ambient is increase in effective ambient temperature from cumulative induced power to DUTs shall not result in devicejunction temperature exceeding maximum temperature shall not be measured in the convection current (above) or downstream (Fan Air) of air greater than 30 CFM (natural convection) may be allowed for the purpose of temperature equalizationwithin high device density burn-in velocity or cooled air shall not be used for the purpose of increasing device up of burn-in racks may occur when ambient is less than specified. When thermal equilibrium has beenreached, or five hours maximum has occurred, the ambient shall be at the specified value. Time accrued prior toreaching specified ambient shall not be chargeable, to the life test the ambient at or beyond the five hour point is not the specified value, a nonconformance shall exist requiringcorrective is not chargeable during the period when specified conditions are not maintained. If device maximum ratings(iflife test, finish the test and use for credit; if shippable, use this criteria)are exceeded and the manufacturer intends tosubmit the lot affected, the product on test must be evaluated by re-starting the burn-in or HTRB from zero hours atthe specified temperature and verifying that the end-point failure rate is typical for this product type from a review ofestablished temperature for HTRB and burn-in shall be controlled to r3 percent of the specified value. (Unlessotherwise specified in ) This temperature shall be maintained within the chamber. Forced air may be used toequalize temperature within the chamber but shall not be used as a coolant to increase device power Bias errors at the power supply source caused by changing power supply loads during temperature transitions shallnot exceed r5 percent of that specified PAGE 9 OF values at the source, during stabilized conditions, shall not exceed r3 percent of the specified apparatus shall be arranged so as to result in the approximate average power dissipation for each devicewhether devices are tested individually or in a group. Bias and burn-in circuitry tolerances should not vary testconditions to individual devices by more than r5 percent of specified variation in individual device characteristics need not be compensated for by burn-in equipment shall be arranged so that the existence of failed or abnormal devices in a group does not negate theeffect of the test for other devices in the group. Periodic verification will assure that specified conditions are beingmaintained. Verification shall be performed, as a minimum, at the starting and end of , stud, or case mounted devices shall be mounted in their normal mounting configuration and the point ofmechanical connection shall be maintained at no less than the specified Destructive tests. Unless otherwise demonstrated, the following MIL-STD-750 tests are classified as destructive:METHOD NUMBERTEST1017Neutron irradiation1019Steady state total dose irradiation1020ESDS classification1021Moisture resistance 1036,1037Intermittent operation life1041Salt atmosphere1042(Condition D)Burn-in/life test for power MOSFETs1046Salt spray1056Thermal shock (glass strain)2017Die shear test2031Soldering heat2036Terminal strength2037Post seal bond strength2075Decap internal visual design verification2077SEMAll other mechanical or environmental tests (other than those listed in ) shall be considered destructive initially, but maysubsequently be considered nondestructive upon accumulation of sufficient data to indicate that the test is nondestructive. Theaccumulation of data from five repetitions of the specified test on the same sample of product, without significant evidence ofcumulative degradation in any device in the sample, is considered sufficient evidence that the test is nondestructive for the deviceof that manufacturer. Any test specified as a 100 percent screen shall be considered nondestructive for the stress level andduration or number of cycles applied as a PAGE 10 OF Nondestructive tests. Unless otherwise demonstrated, the following MIL-STD-750 tests are classified as nondestructive:Method numberTest1001Barometric pressure1022Resistance to solvents1026, 1027Steady-state life1031, 1032High temperature life (non-operating)1038, 1039, 1040Burn-in screen1042 (Condition A, B, and C)Burn-n/life test for power MOSFETs1051 (100 cycles or less)Thermal shock (temperature cycling)1071Hermetic seal tests2006Constant acceleration2016Shock2026Solderability (if the original lead finish is unchanged and if the maximum allowablenumber of reworks is not exceeded.)2052PIND test2056Vibration, variable frequency2066Physical dimensions2069, 2070, 2072, 2073, 2074Internal visual (pre-cap)2071External visual2076Radiographic inspection2081Forward instability shock test (FIST)2082Backward instability shock test (BIST)3101Thermal impedance testing of diodes3103Thermal impedance measurements for IGBTs3104Thermal impedance measurements for GaAs3051, 3052, 3053(with limited supply voltage)Safe operating area (SOA) (condition A for method 3053)3131Thermal resistance (emitter to base forward voltage, emitter-only switchingmethod)4066Surge current4081Thermal resistance of lead mounted diode (forward voltage, switching method)When the junction temperature exceeds the device maximum rated junction temperature for any operation or test (includingelectrical stress test), these tests shall be considered destructive except under transient surge or nonrepetitive fault conditions orapproved accelerated screening when, it may be desirable to allow the junction temperature to exceed the rated junctiontemperature. The feasibility shall be determined on a part by part basis and in the case where it is allowed adequate sampletesting shall be performed to provide the proper reliability PAGE 11 OF Laboratory suitability. Prior to processing any semiconductor devices intended for use in any military system or sub-system, the facility performing the test(s) must be audited by the Defense Electronics Supply Center, Sourcing and QualificationDivision (DESC-ELST) and be granted written Laboratory Suitability status for each test method to be employed. Processing ofany devices by any facility without Laboratory Suitability status for the test methods used shall render the processed DETAILED REQUIREMENTS (NOT APPLICABLE)6. International standardization agreement. Certain provisions of this standard are the subject of international standardizationagreement. When amendment, revision, or cancellation of this standard is proposed which will affect or violate the internationalagreement concerned, the preparing activity will take appropriate reconciliation action through international standardizationchannels, including departmental standardization offices, if :Preparing activity:Navy - EC DLA - ECArmy - ERAir Force - 17(Project 5961-1451)NASA - NAReview activities:Army - AR, ER, MINavy - AS, CG, MC, SHAir Force - 19, 85, 99SUPERSEDES PAGE 12 OF MIL-STD-750D12MIL-STD-750DNUMERICAL INDEXofTEST METHODS13/14MIL-STD-750DNumerical index of test methodsMethod no. TitleEnvironmental tests (1000 series). pressure (reduced). primary photocurrent irradiation procedure (electron beam). resistance. irradiation. 1018Internal water-vapor content. total dose irradiation procedure. discharge sensitivity (ESDS) classification. resistance. to solvents. operation life. operation life (sample plan). life (nonoperating). (nonoperating) life (sample plan). operation life. operation life (sample plan). (for diodes, rectifiers, and zeners). (for transistors). 1040Burn-in (for thyristors (controlled rectifiers)). atmosphere (corrosion). and life test for power MOSFET's or insulated gate bipolar transistors (IGBT). spray (corrosion). 1048Blocking life. 1049Blocking life (sample plan). cycling (air to air). environment stress test. mission temperature cycle. shock (liquid to liquid). measurement, case and stud. point. characteristics tests (2000 series). lead tensile test. 2006Constant acceleration. attach integrity. heat. strength. 2037Bond strength. fatigue. noise. impact noise detection (PIND) test. 2056Vibration, variable frequency. , variable frequency (monitored). 2066Physical dimensions. 2068External visual for nontransparent, glass-encased, double plug, noncavity, axial leaded diodes. visual, power MOSFET's. visual microwave discrete and multichip transistors. and mechanical examination. visual transistor (pre-cap) inspection. 2073Visual inspection for die (semiconductor diode). visual inspection (discrete semiconductor diodes). 2075Decap internal visual design index of test methods - no. TitleMechanical characteristics tests (2000 series) - Continued. electron microscope (SEM) inspection of metallization. 2081Forward instability, shock (FIST). 2082Backward instability, vibration (BIST). 2101DPA procedures for diodes. 2102DPA procedures for wire bonded characteristics tests for bipolar transistors (3000 series). voltage, collector to base. by pulsing. voltage, collector to emitter. 3015Drift. 3020Floating potential. voltage, emitter to base. 3030Collector to emitter voltage. to base cutoff current. to emitter cutoff current. 3051Safe operating area (continuous dc). 3052Safe operating area (pulsed). 3053Safe operating area (switching). to base cutoff current. emitter voltage (saturated or nonsaturated). 3071Saturation voltage and resistance. transfer ratio. input resistance. and thermal resistance measurements (3100 series). impedance testing of diodes. 3103Thermal impedance measurements for insulated gate bipolar transistor (delta gate-emitter on voltage method). 3104Thermal impedance measurements of GaAs MOSFET's (constant current forward-biased gate voltage method). method for thermal resistance of a bridge rectifier assembly. 3126Thermal resistance (collector-cutoff-current method). impedance measurements for bipolar transistors (delta base-emitter voltage method). 3132Thermal resistance (dc forward voltage drop, emitter base, continuous method). 3136Thermal resistance (forward voltage drop, collector to base, diode method). 3141Thermal response time. time constant. 3151Thermal resistance, general. 3161Thermal impedance measurements for vertical power MOSFET's (delta source-drain voltage method). 3181Thermal resistance for frequency tests (3200 series). short-circuit input impedance. short-circuit forward-current transfer ratio. 3211Small-signal open-circuit reverse-voltage transfer ratio. 3216Small-signal open-circuit output admittance. 3221Small-signal short-circuit input admittance. 3231Small-signal short-circuit output admittance. 3236Open circuit output capacitance. capacitance (output open-circuited or short-circuited). 3241Direct interterminal index of test methods - no. TitleLow frequency tests (3200 series) - Continued. figure. response. 3255Large signal power gain. 3256Small signal power gain. unity gain frequency. 3266Real part of small-signal short circuit input frequency tests (3300 series) 3301Small-signal short-circuit forward-current transfer-ratio cutoff frequency. short-circuit forward-current transfer ratio. 3311Maximum frequency of oscillation. 3320RF power output, RF power gain, and collector characteristics tests for MOS field-effect transistors (3400 series) voltage, gate to source. to source voltage or current. 3404MOSFET threshold voltage. to source on-state voltage. voltage, drain to source. reverse current. current. reverse current. drain to source on-state resistance. 3423Small-signal, drain to source on state resistance. 3431Small-signal, common-source, short-circuit, input capacitance. 3433Small-signal, common-source, short-circuit, reverse-transfer capacitance. 3453Small-signal, common-source, short-circuit, output admittance. 3455Small-signal, common-source, short-circuit, forward transadmittance. 3457Small-signal, common-source, short-circuit, reverse transfer admittance. 3459Pulse response (FET). 3461Small-signal, common-source, short-circuit, input admittance. 3469Repetitive unclamped inductive switching. pulse unclamped inductive switching. charge. time test. recovery time (trr) and recovered charge (Qrr) for power MOSFET (drain-to-source) and power rectifierswith trr d 100 ns. operating area for power MOSFET's or insulated gate bipolar transistors. transconductance (pulsed dc method) of power MOSFET's or insulated gate bipolar transistors. 3476Commutating diode for safe operating area test procedure for measuring dv/dt during reverse recovery of powerMOSFET transistors or insulated gate bipolar transistors. of insulated gate bipolar transistor total switching losses and switching times. transistor electrical dose rate test method. 3479Short circuit withstand time. 3490Clamped inductive switching safe operating area for MOS gated power characteristics tests for Gallium Arsenide transistors (3500 series) 3501Breakdown voltage, drain to source. 3505Maximum available gain of a GaAs FET. 35101 dB compression point of a GaAs FET. 3570GaAs FET forward gain (Mag S21). 3575Forward index of test methods - no. TitleElectrical characteristics tests for diodes (4000 series). 4000Condition for measurement of diode static parameters. voltage. current leakage. voltage (diodes). 4022Breakdown voltage (voltage regulators and voltage-reference diodes). 4023Scope display. recovery voltage and time. recovery characteristics. "Q" for voltage variable capacitance diodes. efficiency. current, average. reverse breakdown impedance. forward impedance. charge. current. coefficient of breakdown voltage. current. resistance of lead mounted diodes (forward voltage, switching method).Electrical characteristics tests for microwave diodes (4100 series) loss. 4102Microwave diode capacitance. 4106Detector power efficiency. of merit (current sensitivity). impedance. noise ratio. noise figure and noise figure of the IF amplifier. resistance. wave ratio (SWR). by repetitive pulsing. by single pulse. 4151Rectified microwave diode characteristics tests for thyristors (controlled rectifiers) (4200 series) current. blocking current. blocking current. 4216Pulse response. 4219Reverse gate current. voltage or gate-trigger current. 4223Gate-controlled turn-on time. 4224Circuit-commutated turn-off time. 4225Gate-controlled turn-off time. "on" voltage. rate of voltage characteristics tests for tunnel diodes (4300 series) 4301Junction capacitance. characteristics of tunnel diodes. 4316Series inductance. 4321Negative resistance. 4326Series resistance. 4331Switching index of test methods - no. TitleHigh reliability space application tests (5000 class) lot acceptance testing. 5002Capacitance-voltage measurements to determine oxide quality. 5010Clean room and workstation airborne particle classification and DOCUMENT IMPROVEMENT PROPOSALINSTRUCTIONS1. The preparing activity must complete blocks 1, 2, 3, and 8. In block 1, both the document number and revision letter should be The submitter of this form must complete blocks 4, 5, 6, and The preparing activity must provide a reply within 30 days from receipt of the : This form may not be used to request copies of documents, nor to request waivers, or clarification ofrequirements on current contracts. Comments submitted on this form do not constitute or imply authorization towaive any portion of the referenced document(s) or to amend contractual RECOMMEND A CHANGE:1. DOCUMENT NUMBER MIL-STD-7502. DOCUMENT DATE (YYMMDD)3. DOCUMENT TITLE TEST METHODS FOR SEMICONDUCTOR DEVICES4. NATURE OF CHANGE (Identify paragraph number and include proposed rewrite, if possible. Attach extra sheets as needed.)5. REASON FOR RECOMMENDATION6. SUBMITTERa. NAME (Last, First, Middle initial)b. ORGANIZATIONc. ADDRESS (Include Zip Code)d. TELEPHONE (Include Area Code)(1) Commercial(2) AUTOVON (If applicable)7. DATE SUBMITTED (YYMMDD)8. PREPARING ACTIVITYa. NAMEb. TELEPHONE (Include Area Code)(1) Commercial (2) AUTOVONc. ADDRESS (Include Zip Code)IF YOU DO NOT RECEIVE A REPLY WITHIN 45 DAYS, CONTACT: Defense Quality and Standardization Office 5203 Leesburg Pike, Suite 1403, Falls Church, VA 22041-3466 Telephone (703) 756-2340 AUTOVON 289-2340 DD Form 1426, OCT 89 Previous editions are obsolete 198/290MIL-STD-750D1000 SeriesEnvironmental testsMIL-STD-750DMETHOD PRESSURE (REDUCED)1. Purpose. The purpose of this test is to check the device capabilities under conditions simulating the low pressureencountered in the nonpressurized portions of aircraft in high altitude Apparatus. The apparatus used for the barometric-pressure test shall consist of a vacuum pump and a suitable sealedchamber having means for visual observation of the specimen under test when necessary. A suitable pressure indicator shallbe used to measure the simulated altitude in feet in the sealed Procedure. The specimens shall be mounted in the test chamber as specified and the pressure reduced to the valueindicated in one of the following test conditions, as specified. Previous references to this method do not specify a testcondition; in such cases, test condition B shall be used. While the specimens are maintained at the specified pressure, andafter sufficient time has been allowed for all entrapped air in the chamber to escape, the specimens shall be subjected to thespecified ConditionPressure - MaximumAltitudeInches of mercuryMillimeters of mercuryFeetMetersA - - - - - - - 30,000 9,144B - - - - - - - 50,000 15,240C - - - - - - - 70,000 21,336D - - - - - - - ,000 30,480E - - - - - - - ,000 45,720F - - - - - - 15,000 4,572G - - - - - - X X 10-6656,000200,000 In addition the following is minutes before and during the test, the test temperature shall be +25qC specified voltage shall be applied and monitored over the range from atmospheric pressure to the specifiedminimum pressure and returned so that any device malfunctions, if they exist, will be Failure criteria. A device which exhibits arc-overs, harmful coronas, or any other defect or deterioration that may interferewith the operation of the device shall be considered a Summary. The following conditions must be specified in the detail (see 2.). pressure (see 2.).METHOD Purpose. This test is performed to determine the effectiveness of the seal of component parts. The immersion of thepart under evaluation into liquid at widely different temperatures subjects it to thermal and mechanical stresses which willreadily detect a defective terminal assembly, or a partially closed seam or molded enclosure. Defects of these types can resultfrom faulty construction or from mechanical damage such as might be produced during physical or environmental tests. Theimmersion test is generally performed immediately following such tests because it will tend to aggravate any incipient defects inseals, seams, and bushings which might otherwise escape notice. This test is essentially a laboratory test condition, and theprocedure is intended only as a measurement of the effectiveness of the seal following this test. The choice of fresh or saltwater as a test liquid is dependent on the nature of the component part under test. When electrical measurements are madeafter immersion cycling to obtain evidence of leakage through seals, the use of a salt solution instead of fresh water willfacilitate detection of moisture penetration. This test provides a simple and ready means of detection of the migration ofliquids. Effects noted can include lowered insulation resistance, corrosion of internal parts, and appearance of salt test described is not intended as a thermal-shock or corrosion test, although it may incidentally reveal inadequacies inthese Procedure. The test consists of successive cycles of immersions, each cycle consisting of immersion in a hot bath offresh (tap) water at a temperature of 65qC +5qC,-0qC (149qF +9qF, -0qF) followed by immersion in a cold bath. The number ofcycles, duration of each immersion, and the nature and temperature of the cold bath shall be as indicated in the applicable testcondition listed in table 1011-1, as condition Number of cyclesDuration of eachimmersion (Minutes)Immersion bath (cold)Temperature of cold bath(qC)A - - - - - -215Fresh (tap) water25, +10, -5B - - - - - -215Saturated solution ofsodium chloride , +10, -5C - - - - - -560Saturated solution ofsodium chloride r 3The transfer of specimens from one bath to another shall be accomplished as rapidly as practicable. After completion of thefinal cycle, specimens shall be thoroughly and quickly washed and all surfaces wiped or air-blasted clean and Measurements. Unless otherwise specified, measurements shall be made at least 4 hours, but not more than 24 hours,after completion of the final cycle. Measurements shall be made as Summary. The following details are to be specified in the individual condition letter (see 2). after final cycle allowed for measurements, if other than that specified (see 3). after final cycle (see 3).METHOD PRIMARY PHOTOCURRENT IRRADIATION PROCEDURE (ELECTRON BEAM)1. Purpose. This test procedure establishes the means for measuring the steady-state primary photocurrent (IPH) enerated insemiconductor devices when these devices are exposed to ionizing radiation. In this test method, the test device is irradiated in theprimary electron beam of a linear accelerator (LINAC). Definitions. The following definitions shall apply for this test Primary photocurrent (IPH). The flow of excess charge carriers across a P-N junction due to ionizing radiation creatingelectron-hole pairs in the vicinity of the P-N Measurement interferences. A current measured in the test circuits that does not result from primary photocurrent (seeappendix).2. Ionizing pulse source. The ionizing pulse shall be produced by an electron LINAC. The ionizing pulse shall have dose ratevariations within r15 percent of nominal during the pulse and shall consist of electrons with an energy equal to or greater than 10 Pulse recording equipment. Pulse recording equipment shall be provided that will display and record both the photocurrent andthe pulse-shape monitor signal. It may consist of oscilloscopes with recording cameras, appropriate digitizing equipment, or otherapproved recording equipment. The equipment shall have an accuracy and resolution of five percent of the pulse width and maximumamplitude of the ionizing Test circuits. One of the following test circuits shall be selected, radiation-shielded, and close enough to the DUT in order to meetthe requirements of Resistor sampling circuits. The resistor sampling circuits shall be as shown on figure Current transformer circuit. The current transformer circuit shall be as shown on figure Irradiation pulse-shape monitor. One of the following devices shall be used to develop a signal proportional to the dose ratedelivered to the DUT. Any time constants which degrade the linear response of the monitor signal shall be less than 10 percent of thebeam pulse width. The dose rate at the monitor shall be proportional to the dose rate at the DUT and the variation from proportionalityshall not exceed r3 Signal diode. The signal diode selected shall have a response that is linear within r5 percent of the dose rate over the selectedirradiation range. Depending on the sensitivity of the diode, it may be positioned at a point within the beam from the ionizing source atwhich it will remain in the linear region. The signal diode shall be placed in one of the test circuits described in , and it shall be backbiased at not more than fifty percent of the diode breakdown P-type-intrinsic-N-type (P-I-N) diode. A P-I-N diode shall be used as stated in Current transformer. A transformer with a hollow central axis that shall be mounted around the output of the ionizing Secondary-emission monitor. The secondary-emission monitor shall consist of a thin foil mounted in a chamber evacuated Pa ( mmHg) which is located in the path of the beam from the ionizing source. The foil shall be biased negatively with respectto ground, or shielded with positively biased Dosimeter. The dosimeter shall be used to calibrate the output of the pulse-shape monitor in terms of dose rate. The dosimetertype shall be a commercial thermoluminescent detector (TLD), thin calorimeter or other system as specified. The dosimetrymeasurement technique shall be accurate to r20 of 5MIL-STD-750 = 1,000 :, 5 = 5 :, 1 = 15 PF, 5 = .01 PF, 5 = Characteristic termination for coaxial B shall be used for large photocurrents (those for which more than 10 percent of the bias appears across resistor RTin circuit A). for circuit for circuit B:FIGURE 1015-1. Resistor sampling = 1,000 :, 5 = 15 PF, 5 = .01 PF, 5 = Characteristic termination for coaxial calculation:FIGURE 1015-2. Current transformer General. The test facility shall select a test fixture and pulse shape monitor. The test fixture and monitor shall be aligned with thebeam from the ionizing source. In addition, any shielding, collimation, or beam scattering equipment shall be properly positioned. Ifrepositioning of any equipment or the test circuit is required to accomplish the device testing, the repositioning shall be demonstrated tobe reliable and Test circuit check-out. The ionizing source shall be pulsed either with an empty device package or without the DUT in the testcircuit and with all required bias applied. The ionizing source shall be adjusted to supply the dose rate required for this test. Therecorded current from the pulse recording equipment shall be no more than 10 percent of the steady-state photocurrent expected to bemeasured for this test (see ). If this condition is not met, see Ionizing source calibration. Mount the selected dosimeter in place of the DUT. Pulse the ionizing source, record the pulse-shapemonitor signal, and determine the radiation dose measured by the dosimeter. Calculate a dose rate factor as follows:This measurement shall be repeated five times, and the average of the six dose rate factors obtained shall be the dose rate factor usedfor the test. One dosimeter may be used repetitively if the dose is read for each Device Mounting. Mount the DUT in the beam from the ionizing source and connect it to the rest of the test circuit. The bias appliedshall be as specified in the device specification; or if not specified, the bias shall be fifty percent of the specified breakdown voltage of Dose rate. Either adjust the ionizing source beam current or use an alternate method ( , scatterers or a different samplelocation) to obtain the specified dose rate r20 percent. Pulse the ionizing source and record the pulse-shape monitor signal and thephotocurrent signal from the Calculate photocurrent. The steady-state photocurrent shall be calculated as expressed on the figure selected for the test circuitin Verify test circuit. Check the current recorded in the test circuit in and verify that the value of the current does not exceed 10percent of the photocurrent recorded in Test circuit checkout. Repeat the device test (see ) for each dose rate that is required by the device specification. Thecalibration (see ) shall be performed for each dose rate to be tested. The test circuit checkout (see ) shall be performed when anew device type is tested or when any change is made in the position of the test circuit or DUT supporting Summary. The following conditions shall be specified in the detail pulse width requirements of the ionizing pulse source. (The pulse width must exceed the semiconductor minority lifetimeby at least a factor of 2.) bias applied to the device (see ). irradiation dose rate(s) applied (see ). required, any total dose required, a description of the placement of the device in the beam with respect to the required, for multi-junction devices, the device terminals that are to be required, the procedure for approval of the test facility and INTERFERENCESThe following problems commonly arise when electronics are tested in a radiation environment. Most of these interferences are presentwhen the test circuit is irradiated under bias with the DUT Air irradiation pulse can ionize the air around the test circuit and provide a spurious conduction path. The air ionization contribution tothe signal is proportional to the applied bias. The effect of air ionization is minimized by reducing the circuit components exposed to thebeam pulse, by coating exposed leads with a thick nonconducting layer or by performing the test in a Secondary beam pulse irradiating any electrical lead or component can cause a net charge to enter or leave the exposed surfaces. Thisspurious current alters the measured photocurrent. Secondary emission effects are reduced by minimizing the circuit componentsexposed to the direct Perturbed irradiation material exposed to the beam pulse will scatter and modify the incident radiation of the beam. A nearby DUT or dosimeter will thenbe exposed to a noncharacterized and unexpected form of radiation. These field perturbations are reduced by minimizing the mass of thestructure supporting the DUT and the dosimeter that is exposed to the beam. All materials should have a low atomic number; ,plastics and RF ionizing pulse source discharges large amounts of electromagnetic energy at the same time the photocurrent is being electrical practice is necessary to eliminate resonant structure, noise pick-up on signal cables, common mode pick-up, groundloops, and similar 1016INSULATION RESISTANCE1. The device shall be tested in accordance with method 302, 10161/2MIL-STD-750DMETHOD IRRADIATION1. Purpose. The neutron irradiation test is performed to determine the susceptibility of discrete semiconductor devices to degradationin the neutron environment. This test is destructive. Objectives of the test detect and measure the degradation of critical semiconductor device electrical characteristics as a function of determine if specified semiconductor device electrical characteristics are within specified limits after exposure to aspecified level of neutron fluence (see 4).2. Test instruments. Test instrumentation to be used in the radiation test shall be standard laboratory electronic test instrumentssuch as power supplies, digital voltmeters and picoammeters, capable of measuring the electrical parameters required. Parameter testmethods and calibration shall be in accordance with Radiation source. The radiation source used in the test shall be in a TRIGA Reactor or a Fast Burst Reactor. Operation may bein either pulse or steady-state repetitive pulse conditions as appropriate. The source shall be one that is acceptable to the Dosimetry threshold activation foils such as 32S, 54Fe, and activation foil counting and TLD readout Dosimetry Neutron fluence. The neutron fluence used for device irradiation shall be obtained by measuring the amount of radioactivityinduced in a fast-neutron threshold activation foil such as 32S, 54Fe, or 58Ni, irradiated simultaneously with the device. A standardmethod for converting the measured radioactivity in the specific activation foil employed into a neutron fluence is given in the followingDepartment of Defense adopted ASTM standards:E263Standard Test Method for Measuring Fast-Neutron Flux by Radioactivation of Test Method for Measuring Fast-Neutron Flux by Radioactivation of Test Method for Measuring Fast-Neutron Flux by Radioactivation of conversion of the foil radioactivity into a neutron fluence requires a knowledge of the neutron spectrum incident on the foil. If thespectrum is not known, it shall be determined by use of the following DoD adopted ASTM standards, or their equivalent:E720Standard Guide for Selection of a Set of Neutron-Activation Foils for Determining Neutron Spectraused in Radiation-Hardness Testing of Method for Determining Neutron Energy Spectra with Neutron-Activation Foils forRadiation-Hardness Testing of Practice for Characterizing Neutron Energy Fluence Spectra in Terms of an EquivalentMonoenergetic Neutron Fluence for Radiation-Hardness Testing of of 3MIL-STD-750DOnce the neutron energy spectrum has been determined and the equivalent monoenergetic fluence calculated, then an appropriatemonitor foil (such as 32S, 54Fe, or 58Ni) should be used in subsequent irradiations to determine the neutron fluence as discussed inE722. Thus, the neutron fluence is described in terms of the equivalent monoenergetic neutron fluence per unit monitor response. Useof a monitor foil to predict the equivalent monoenergetic neutron fluence is valid only if the energy spectrum remains If absorbed dose measurements of the gamma-ray component during the device test irradiations are required, then suchmeasurements shall be made with CaF2 TLDs, or their equivalent. These TLDs shall be used in accordance with the recommendationsof the following DoD adopted ASTM standard:E668Standard Practice for the Application of Thermoluminescence-Dosimetry (TLD) Systems forDetermining Absorbed Dose in Radiation-Hardness Testing of Electronic Safety requirements. Neutron irradiated parts may be radioactive. Handling and storage of test specimens or equipmentsubjected to radiation environments shall be governed by the procedures established by the local Radiation Safety Officer or HealthPhysicist. NOTE:The receipt, acquisition, possession, use, and transfer of this material after irradiation is subject to theregulations of the Nuclear Regulatory Commission, Radioisotope License Branch, Washington,DC 20555. A by-product license is required before an irradiation facility will expose any test devices.( Code, see 10 CFR 30-33.) Test samples. Unless otherwise specified, a test sample shall be randomly selected and consist of a minimum of 10 parts. Allsample parts shall have met all the requirements of the governing specification for that part. Each part shall be serialized to enable preand post test identification and Electrical tests. Pre-exposure electrical tests shall be performed on each part as required. Where delta parameter limits arespecified, the pre-exposure data shall be Exposure set-up. Each device shall be mounted unbiased and have its terminal leads either all shorted or all open. For MOSdevices all leads shall be shorted. An appropriate mounting fixture which will accommodate both the sample and the required dosimeters(at least one actuation foil and one CaF2 TLD) shall be used. The configuration of the mounting fixture will depend on the type of reactorfacility used and should be discussed with reactor facility personnel. Test devices shall be mounted such that the total variation offluence over the entire sample does not exceed 20 percent. Reactor facility personnel shall determine both the position of the fixture andthe appropriate pulse level or power time product required to achieve the specified neutron fluence Exposure. The test devices and dosimeters shall be exposed to the neutron fluence as specified. The exposure level may beobtained by operating the reactor in either the pulsed or power mode. If multiple exposures are required, the post-irradiation electricaltests shall be performed (see ) after each exposure. A new set of dosimeters are required for each exposure level. Since the effectsof neutrons are cumulative, each additional exposure level will have to be determined to give the specified total accumulated fluence. Allexposures shall be made at 20 C 10 C and shall be correlated to a 1 MeV equivalent Electrical tests. Test devices shall be removed only after clearance has been obtained from the health physicist at the testfacility. The temperature of the sample devices shall be maintained at +20 C 10 C from the time of the exposure until the post-electricaltests are made. The post-exposure electrical tests shall be made within 24 hours after the completion of the exposure. If the residualradioactivity level determined by the local radiation safety officer is too high for device handling purposes, the elapsed time beforepost-test electrical measurements are made shall be extended to 1 week or remote testing shall be utilized. All required data must berecorded for each device after each Failure analysis. Devices which exhibit anomalous behavior ( , non-linear degradation of 1/ ) shall be subjected to Reporting. In reporting the results of radiation tests on discrete devices, adequate identification of the devices is essential. As aminimum, the report shall include the device type number, serial number, the manufacturer, controlling specification, the date code, andother Part or Identifying Numbers (PINs) provided by the manufacturer. Each data sheet shall include radiation test date, electrical testconditions, radiation test levels, and ambient conditions as well as the test data. When other than specified electrical test circuits areemployed, the parameter measurement circuits shall accompany the data. Any anomalous incidents during the test shall be fullyexplained in footnotes to the Summary. The following conditions shall be specified in the request for test or when applicable, the detail of each device type to be tested if other than specified in parameters to be measured in pre- and post-exposure for pass, fail, record actions on tested for anomalous behavior exposure instrument dosimetry requirements if other than temperature if other than specified for data reporting and submission, where 1018INTERNAL WATER-VAPOR CONTENT1. Purpose. The purpose of this test is to measure the water-vapor content of the atmosphere inside a metal or ceramichermetically-sealed device. It can be destructive (procedures 1 and 2) or nondestructive (procedure 3).2. Apparatus. The apparatus for the internal water-vapor content test shall be as follows for the chosen Procedure 1. (Procedure 1 measures the water-vapor content of the device atmosphere by mass spectrometry.) The apparatusfor procedure 1 shall consist mass spectrometer capable of reproducibly detecting the specified moisture content for a given volume package with afactor of 10 sensitivity safety margin ( , for a specified limit of 5,000 ppmv, .01 cc, the mass spectrometer shall demonstratea 500 ppmv or less absolute sensitivity to moisture for a package volume of .01 cc). The smallest volume shall be consideredthe worst case. The calibration of the mass spectrometer shall be accomplished at the specified moisture limit ( 20 percent)using a package simulator which has the capability of generating at least three known volumes of gas 10 percent on arepetitive basis by means of a continuous sample volume purge of known moisture content 10 percent. Moisture contentshall be established by the standard generation techniques ( , 2 pressure, divided flow, or cryogenic method). The absolutemoisture shall be measured by an NIST calibrated moisture dew point analyzer at least once every two years. The NISTcalibrated dew pointer shall be returned to the National Institute of Standards Technology at least once each year forrecalibration. Calibration records shall be kept on a daily basis and made available to DCAS personnel. Gas analysis resultsobtained by this method shall be considered valid only in the moisture range or limit bracketed by at least two (volume orconcentration) calibration points ( , 5,000 ppmv between .01 - .1 cc or 1,000 - 5,000 ppmv between .01 - .1 cc). A best fitcurve shall be used between volume calibration points. Corrections of sensitivity factors deviating greater than 10 percentfrom the mean between calibration points shall be vacuum opening chamber which can contain the device and a vacuum transfer passage connecting the device to the massspectrometer of The transfer passage shall be maintained at +125 C 5 C. The fixturing in the vacuum openingchamber shall position the specimen as required by the piercing arrangement of , and maintain the device at +100 C 5 C for a minimum of 10 minutes prior to piercing arrangement functioning within the opening chamber or transfer passage of , which can pierce the specimenhousing (without breaking the mass spectrometer chamber vacuum and without disturbing the package sealing medium), thusallowing the specimen's internal gases to escape into the chamber and mass : A sharp-pointed piercing tool, actuated from outside the chamber wall via a bellows to permit movement, should beused to pierce both metal and ceramic packages. For ceramic packages, the package lid or cover should belocally thinned by abrasion to facilitate localized Procedure 2. (Procedure 2 measures the water-vapor content of the device atmosphere by integrating moisture picked up by a drycarrier gas at +50 C.) The apparatus for procedure 2 shall consist integrating electronic detector and moisture sensor capable of reproducibly detecting a water-vapor content of 300 50ppmv moisture for the package volume being tested. This shall be determined by dividing the absolute sensitivity inmicrograms H20 by the computed weight of the gas in the DUT, and then correcting to 10181 of 4MIL-STD-750Db. A piercing chamber or enclosure, connected to the integrating detector of , which will contain the device specimen andmaintain its temperature at +100 C 5 C during measurements. The chamber shall position the specimen as required by thepiercing arrangement. The piercing mechanism shall open the package in a manner which will allow the contained gas to bepurged out by the carrier gas or removed by evacuation. The sensor and connection to the piercing chamber will bemaintained at a temperature of +50 C 2 Procedure 3. (Procedure 3 measures the water-vapor content of the device atmosphere by measuring the response of a calibratedmoisture sensor or an IC chip which is sealed within the device housing, with its electrical terminals available at the package exterior.)The apparatus for procedure 3 shall consist of one of the moisture sensor element and readout instrument capable of detecting a water-vapor content of 300 50 ppmv while sensoris mounted inside a sealed runs on the DUT isolated by back-biased diodes which when connected as part of a bridge network can detect2,000 ppmv within the cavity. The chip shall be cooled in a manner such that the chip surface is the coolest surface in thecavity. The device shall be cooled below dew point and then heated to room temperature as one complete test :Suitable types of sensors may include (among others) parallel or interdigitated metal stripes on an oxidized silicon chip, andporous anodized-aluminum structures with gold-surface conductivity sensors may not be used in metal packages without external package wall insulation. When used, the sensor shallbe the coolest surface in the cavity. It should be noted that some surface conductivity sensors require a higher ionic content thanavailable in ultraclean CERDIP packages. In any case, correlation with mass spectrometer procedure 1 shall be established by clearlyshowing that the sensor reading can determine whether the cavity atmosphere has more or less than the specified moisture limit at+100 Procedure. The internal water-vapor content test shall be conducted in accordance with the requirements of procedure 1,procedure 2, or procedure 3. Devices containing desiccants or organics shall be prebaked for 12 to 24 hours at +100 C 5 C prior to hotinsertion into Procedure 1. The device shall be hermetic in accordance with test method 1014, and free from any surface contaminants whichmay interfere with accurate water-vapor content device insertion, the device and chamber shall be pumped down and baked out at a temperature of +100 C 5 C until thebackground pressure level will not prevent achieving the specified measurement accuracy and sensitivity. After pumpdown, the devicecase or lid shall be punctured and the following properties of the released gases shall be measured, using the mass increase in chamber pressure as the gases are released by piercing the device package. A pressure rise of less than 50percent of normal for that package volume and pressurization may indicate that (1) the puncture was not fully accomplished,(2) the device package was not sealed hermetically, or (3) does not contain the normal internal water-vapor content of the released gases, as a proportion (by volume) of the total gas proportions (by volume) of the other following gases: N2, He, Mass 69 (fluorocarbons), O2, Ar, H2, CO2, CH4, and othersolvents, if available. Calculations shall be made and reported on all gases present greater than one percent by volume. Datareduction shall be performed in a manner which will preclude the cracking pattern interference from other gas specie in thecalculations of moisture content. Data shall be corrected for any system dependent matrix effects such as the presence ofhydrogen in the internal Failure device which has a water-vapor content greater than the specified maximum value shall constitute a device which exhibits an abnormally low total gas content, as defined in , shall constitute a failure, if it is not a device may be replaced by another device from the same population; if the replacement device exhibits normal totalgas content for its type, neither it nor the original device shall constitute a failure for this analysis on devices containing desiccants or organics shall be terminated after 95 percent of the gas has been analyzedin a dynamic measurement system or data shall be taken after pressure has stabilized for a period of two minutes in a staticsystem or in any manner which approaches the true measurement of ambient moisture in equilibrium at +100 C within Procedure 2. The device shall be hermetic in accordance with test method 1014, and free from any surface contaminants whichmay interfere with accurate water-vapor content device insertion into the piercing chamber, gas shall be flowed through the system until a stable base-line value of the detectoroutput is attained. With the gas flow continuing, the device package shall then be pierced so that a portion of the purge gas flows throughthe package under test and the evolved moisture integrated until the base-line detector reading is again reached. An alternative allows thepackage gas to be transferred to a holding chamber which contains a moisture sensor and a pressure indicator. System is calibrated byinjecting a known quantity of moisture or opening a package of known moisture Failure device which has a water-vapor content (by volume) greater than the specified maximum value shall constitute a removal from the piercing chamber, the device shall be inspected to ascertain that the package has been fully opened. Adevice package which was not pierced shall constitute a failure, if the test is not performed on another device from the samepopulation; if this retest sample or replacement is demonstrated to be pierced and meets the specified water-vapor contentcriteria, the specimen shall be considered to have passed the package which is a leaker in the purge case will be wet and counted as a failure. In the case of evacuation, a normalpressure rise shall be measured as in Procedure 3. The moisture sensor shall be calibrated in an atmosphere of known water-vapor content, such as that established bya saturated solution of an appropriate salt or dilution flow stream. It shall be demonstrated that the sensor calibration can be verified afterpackage seal or that post seal calibration of the sensor by lid removal is an acceptable moisture sensor shall be sealed in the device package or, when specified, in a dummy package of the same type. This sealing shallbe done under the same processes, with the same die attach materials and in the same facilities during the same time period as thedevice population being water-vapor content measurement shall be made, at +100 C or below, by measuring the moisture sensor response. Correlation withprocedure 1 shall be accomplished before suitability of the sensor for procedure 3 is granted. It shall be shown the package ambient andsensor surface are free from any contaminating materials such as organic solvents which might result in a lower than usual Failure criteria. A specimen which has a water-vapor content greater than the specified maximum value shall constitute a 10183MIL-STD-750D4. Implementation. Suitability for performing method 1018 analysis is granted by the qualifying activity for specific limits and 1018 calibration procedures and the suitability survey are designed to guarantee 20 percent lab-to-lab correlation in making adetermination whether the sample passes or fails the specified limit. Water vapor contents reported either above or below the (watervapor content - volume) range of suitability are not certified as correlatable values. This out of specification data has meaning only in arelative sense and only when one laboratory's results are being compared. Suitability status has been granted for a specification limit of5,000 ppmv and package volumes falling between .01 cc and .85 cc. The range of suitability for each laboratory will be extended by thequalifying activity when the analytical laboratories demonstrate an expanded capability. Information on current analytical laboratorysuitability status can be obtained by writing DSCC/VAT, 3990 E. Broad Street, Columbus, OH Summary. The following details shall be specified in the applicable acquisition procedure (1, 2, or 3) when a specific procedure is to be used (see 3.). maximum allowable water-vapor content falling within the range of suitability as specified in test method 5005, 5008, 10184MIL-STD-750DMETHOD TOTAL DOSE IRRADIATION PROCEDURE1. Purpose. This test procedure defines the requirements for testing discrete packaged semiconductor devices for total dose effectsby ionizing radiation from a Cobalt-60 (60Co) gamma ray source. This procedure includes only steady-state irradiations, and is notapplicable to pulse type irradiations. This test may produce severe degradation of the electrical properties of irradiated Definitions. Definitions of terms used in this procedure are given tests: Electrical measurements made on devices during radiation in-flux tests: Electrical measurements made on devices at any time other than during tests: Electrical measurements made on devices which are physically removed from the irradiation location for radiation effects: The changes in the electrical parameters of a device or integrated circuit results fromradiation-induced charge. It is also referred to as total dose Apparatus. The apparatus shall consist of the radiation source, electrical test instrumentation, test circuit board(s), cable,interconnect board or switching system, if used, and appropriate dosimetry measurement system, if used. Adequate precautions shall beobserved to obtain an electrical measurement system with sufficient insulation, ample shielding, satisfactory grounding, and with suitablelow noise from the main power Radiation source. The radiation source used in the test shall be the uniform field of a Cobalt-60 gamma ray source. Unlessotherwise specified, uniformity of the radiation field in the volume where devices are irradiated shall be 10 percent as measured by thedosimetry system. Changes in geometry from one test to another require remeasurement of the field Cobalt-60 source. The gamma ray field of a Cobalt-60 source shall be calibrated at least every three years to an uncertainty ofno more than 5 percent as measured with an appropriate dosimetry system whose calibration is traceable to the NIST. Corrections forCobalt-60 source decay shall be made Dosimetry system. The gamma ray field of the radiation source shall be characterized by appropriate dosimetry (traceable toNIST) methods prior to irradiation of test devices. The following DoD adopted American Society for Testing and Materials (ASTM)standards or their equivalents shall be used:ANSI/ASTM E 666-Standard Method for Calculation of Absorbed Dose from Gamma or X E 66-Standard Practice for the Application of Thermoluminescence-Dosimetry (TLD) Systems forDetermining Absorbed Dose in Radiation-Hardness Testing of Electronic E 1250-Standard Method for Application of Ionization Chambers to Assess the Low Energy GammaComponent of Cobalt 60 Irradiators Used in Radiation Hardness Testing of Silicon electronic E 1275-Standard Practice for Use of a Radiochromic Film Dosimetry E 1249-Minimizing Dosimetry Errors in Radiation Hardness Testing of Silicon Electronic industry standards address the conversion of absorbed dose from one material to another and the proper use of variousdosimetry systems. 1/______1/ Copies may be obtained from ASTM, 1916 Race Street, Philadelphia, PA of Electrical test instruments. All instrumentation used for electrical measurements shall have stability, accuracy, and resolutionrequired for accurate measurement of the electrical parameters. Any instrumentation required to operate in a radiation environment above10 REM per hour shall be appropriately shielded, or the radiation level must be less than the instrumentation manufacturersrecommended Test circuit board(s). Devices to be irradiated shall be mounted on or connected to circuit boards together with any associatedcircuitry necessary for device biasing during irradiation or for in-site measurements. Unless otherwise specified, all device input terminalsand any others which may affect the radiation response shall be electrically connected during irradiation, , not left floating. Thegeometry and materials of the completed board shall allow uniform irradiation of the DUTs. Good design and construction practices shallbe used to prevent oscillations, minimize leakage currents, prevent electrical damage, and obtain accurate measurements. All apparatusused repeatedly in radiation fields shall be checked periodically for physical or electrical degradation. Components which are placed onthe test circuit board, other than DUTs, shall be insensitive to the accumulated radiation, or they shall be shielded from the radiation testfixtures, shall be made in such a way that materials will not disturb the uniformity of the radiation field intensity at the Interconnect or switching system. This system shall be located external to the radiation environment location, and provides theinterface between the test instrumentation and the DUTs. It is part of the entire test system and subject to the limitation specified in leakage between Procedure. The test devices shall be irradiated as specified by a test plan. This plan shall specify the device description, radiationconditions, device bias conditions, dosimetry system operating conditions and measurements, and Sample selection. Unless otherwise specified, the test samples shall be randomly selected from the parent population andidentically packaged. Each part shall be individually identifiable to enable pre- and postirradiation comparison. For device types which areESD-sensitive, proper handling techniques shall be used to prevent damage to the devices. Only devices which have passed theelectrical specification as defined in the test plan shall be submitted to radiation Dosimetry measurements. The radiation field intensity at the location of the DUT shall be determined prior to testing by dosimetryor by source decay correction calculations, as appropriate, to assure conformance to test level and uniformity requirements. The dose tothe DUT shall be determined one of two ways: (1) by measurement during the irradiation with an appropriate dosimeter, or (2) bycorrecting a previous dosimetry value for the decay of the Co 60 source intensity in the intervening time. Appropriate correction shall bemade to convert the measured or calculated dose in the dosimeter material to the dose in the Lead/aluminum (Pb/A1) container. Test specimens shall be enclosed in a Pb/A1 container to minimize dose enhancement effectscaused by low-energy, scattered radiation. A minimum of mm Pb, surrounding an inner shield of at least mm A1, is Pb/A1 container produces an approximate charged particle equilibrium for S1 and for TLDs such as CaF2. The radiation fieldintensity shall be measured inside the Pb/A1 container (1) initially, (2) when the source is changed, or (3) when the orientation ofconfiguration of the source, container, or test-fixture is changed. This measurement shall be performed by placing a dosimeter ( , aTLD) in the device-irradiation container at the approximate test-device position. If it can be demonstrated that low-energy scatteredradiation is small enough that it will not cause dosimetry errors due to dose enhancement, the Pb/A1 container may be Radiation level(s). The test devices shall be irradiated to the dose level(s) specified in the test plan within 10 percent. If multipleirradiations are required for a set of test devices, then the postirradiation electrical parameter measurements shall be performed aftereach Radiation dose Condition A. The dose-rate range shall be between 50 and 2,000 rads (Si)/s ( and 20 Gy(Si)/s) for 60 Co. 2/ The dose ratesmay be different for each radiation dose level in a series; however, the dose rate shall not vary by more than 10 percent during The SI unit for the quantity absorbed dose is the gray, symbol Gy. 100 rad = 1 Condition B. As an alternative, the test may be performed at the dose rate of the intended application, if this is agreed to by theacquisition Temperature requirements. Since radiation effects are temperature dependent, DUTs shall be irradiated in an ambienttemperature of +24 C 6 C as measured at a point in the test chamber in close proximity to the test fixture. The electrical measurementsshall be performed in an ambient temperature of +25 C 5 C. If devices are transported to and from a remote electrical measurementsite, the temperature of the test devices shall not be allowed to increase by more than +10 C from the irradiation environment. If any othertemperature range is required, it shall be Electrical performance measurements. The electrical parameters to be measured and functional tests to be performed shall bespecified in the test plan. As a check on the validity of the measurement system and pre- and postirradiation data, at least one controlsample shall be measured using the operating conditions provided in the governing device specifications. For automatic test equipment(ATE), there is no restriction on the test sequence provided that the rise in the device junction temperature is minimized. For manualmeasurements, the sequence of parameter measurements shall be chosen to allow the shortest possible measurement period. When aseries of measurements is made, the tests shall be arranged so that the lowest power dissipation in the device occurs in the earliestmeasurements and the power dissipation increases with subsequent measurements in the sequence. The pre- and postirradiationelectrical measurements shall be done on the same measurement system and the same sequence of measurements shall be maintainedfor each series of electrical measurements of devices in a test sample. Pulse-type measurements of electrical parameter should be usedas appropriate to minimize heating and subsequent annealing Test conditions The use of in-flux or not in-flux shall be specified in the test plan. (This may depend on the intended applicationfor which the data is being obtained.) The use of in-flux testing may help to avoid variations introduced by postirradiation time dependenteffects. However, errors may be incurred for the situation where a device is irradiated in-flux with static bias, but where the electricaltesting conditions require the use of dynamic bias for a fraction of the total irradiation period. Not-in-flux testing generally allows for morecomprehensive electrical testing, but can be misleading if significant postirradiation time dependent effects In-flux testing. Each test device shall be checked for operation within specifications prior to being irradiated. After the entiresystem is in place for the in-flux radiation test, it shall be checked for proper interconnections, leakage (see ), and noise level. Toassure the proper operation and stability of the test setup, a control device with known parameter values shall be measured at alloperational conditions called for in the test plan. This measurement shall be done either before the insertion of test devices or uponcompletion of the irradiation after removal of the test devices or Remote testing. Unless otherwise specified, the bias shall be removed and the device leads placed in conductive foam (orsimilarly shorted) during transfer from the irradiation source to a remote tester and back again for further irradiation. This minimizespostirradiation time dependent Bias and loading conditions. Bias conditions for test devices during irradiation shall be within 5 percent of those specified bythe test plan. (If known, the bias applied to the test devices shall be selected to produce the greatest radiation induced damage or theworst-case damage for the intended application.) The specified bias shall be maintained on each device in accordance with the test shall be checked immediately before and after irradiation. Care shall be taken in selecting the loading such that the rise in thejunction temperature is Postirradiation procedure. Unless otherwise specified, the following time intervals shall be time from the end of an irradiation to the start of electrical measurements shall be a maximum of one time to perform the electrical measurements and to return the devices for a subsequent irradiation, if any, shallbe within two hours of the end of the prior minimize time dependent effects, these intervals shall be as short as possible. The sequence of parameter measurements shall bemaintained constant through the test Test report. As a minimum, the report shall include the device type number, CAGE code of the manufacturer, package type,controlling specification, date code, and any other PINs given by the manufacturers, the bias conditions during radiation, the radiationlevel, time, temperature, and the pre- and postirradiation recorded readings. The following information is available on request only and isnot a requirement for the data work sheet shall include the test date, the radiation source used, the bias conditions during irradiation,the ambient temperature around the devices during irradiation and electrical testing, the duration of eachirradiation, the time between irradiation and the start of the electrical measurements, the duration of the electricalmeasurements, and the time to the next irradiation when step irradiations are used, the irradiation dose rate,electrical test conditions, dosimetry system and procedures, and the radiation test levels. The pre- andpostirradiation data shall be recorded for each part and retained with the parent population data in accordance withthe requirements of MIL-S-19500. Any anomalous incidents during the test shall be fully documented bias circuit, parameter measurements circuits, the layout of the test apparatus with details of distances andmaterials used, and electrical noise and current leakage of the electrical measurement system for in-flux testing,shall be reported using drawings or diagrams as Summary. The following details shall be specified in the applicable acquisition document as number(s), quantity, and governing specification (see ). dosimetry requirements (see ). test levels including dose and dose rate (see and ). , electrical test, and transport temperature; if other than as specified in parameters to be measured and device operating conditions during measurement (see ). conditions, , in-flux or not-in-flux type tests (see ). conditions for devices during irradiation (see ). intervals of the postirradiation measurements (see ). required to be delivered with devices (see ).METHOD DISCHARGE SENSITIVITY (ESDS) CLASSIFICATION1. Purpose. This method establishes the procedure for classifying semiconductors according to their susceptibility to damage ordegradation by exposure to electrostatic discharge (ESD). This classification is used to specify appropriate packaging and handlingrequirements in accordance with MIL-S-19500, and to provide classification data to meet the requirements of Definitions. The following definitions shall apply for the purposes of this test ESD. A transfer of electrostatic charge between two bodies at different electrostatic Test apparatus. ESD pulse simulator and DUT socket equivalent to the circuit of figure 1020-1, and capable of supplying pulseswith the characteristics required by figure Measurement equipment. Equipment including an oscilloscope and current probe to verify conformance of the simulator outputpulse to the requirements of figure Oscilloscope and amplifier. The oscilloscope and amplifier combination shall have a 350 MHz minimum bandwidth and a visualwriting speed of 4 cm/ns Current probe. The current probe shall have a minimum bandwidth of 350 MHz ( , Tektronix CT-1 at 1,000 MHz). Charging of voltage probe. The charging voltage probe shall have a minimum input resistance of 1,000 M and a division ratio of4 percent maximum ( , HP 34111A). Calibration. Periodic calibration shall include but not be limited to the Charging voltage. The meter used to display the simulator charging voltage shall be calibrated to indicate the actual voltage atpoints C and D of figure 1020-1, over the range specified in table Effective capacitance. Effective capacitance shall be determined by charging C1 to the specified voltage (see table 1020-I), withno device in the test socket and the test switch open, and by discharging C1 into an electrometer, coulombmeter, or calibrated capacitorconnected between points A and B of figure 1020-1. The effective capacitance shall be 100 pF 10 percent over the specified voltagerange and shall be periodically verified at 1,000 volts. (NOTE: A series resistor may be needed to slow the discharge and obtain a validmeasurement.) Current waveform. The procedure of shall be performed for each voltage step of table 1020-I. The current waveform at eachstep shall meet the requirements of figure Qualification. Apparatus acceptance tests shall be performed on new equipment or after major repair. Testing shall include butnot be limited to the Current waveform verification. Current waveform shall be verified at every pin of each test fixture using the pin nearest terminalB (see figure 1020-1) as the reference point. All waveforms shall meet the requirements of figure 1020-2. The pin pair representing theworst case (closest to the limits) waveform shall be identified and used for the verification required by Test circuit. Classification testing shall be performed using a test circuit equivalent to figure 1020-1 to produce the waveformshown on figure of Test temperature. Each device shall be stabilized at room temperature prior to and during ESD classification testing. ESD classification testing of devices shall be considered ESD simulator current waveform verification. To ensure proper simulator operation, the current waveform verification procedureshall be done, as a minimum, at the beginning of each shift when ESD testing is performed, or prior to testing after each change of thesocket/board, whichever is sooner. At the time of initial facility certification and recertifications, photographs shall be taken of thewaveforms observed as required by through and be kept on file for purposes of audit and comparison. (Stored digitizedrepresentations of the waveforms are acceptable in place of photographs.) the DUT socket installed on the simulator, and with no DUT in the socket, place a short (see figure 1020-1) across twopins of the DUT socket and connect one of the pins to simulator terminal A and the other pin to terminal the current probe around the short near terminal B (see figure 1020-1). Set the simulator charging voltage source VS to 4,000 volts corresponding to step 4 of table a simulator pulse and observe the leading edge of the current waveform. The current waveform shall meet the risetime, peak current, and ringing requirements of figure a simulator pulse again and observe the complete current waveform. The pulse shall meet the decay time and ringingrequirement of figure the above verification procedure using the opposite polarity (VS = 4,000 volts). is recommended that the simulator output be checked to verify that there is only one pulse per initiation, and that there is nopulse while capacitor C1 is being charged. To observe the recharge transient, set the trigger to the opposite polarity, increasethe vertical sensitivity by approximately a factor of 10, and initiate a 1020-I. Simulator charging voltage (VS) steps versus peak current (IP). ||||| Step| VS (volts)| IP (amperes)|| | | |||||| 1| 500| || 2| 1,000| || 3| 2,000| || 4| 4,000| || | | | Classification sample of devices (see ) shall be characterized for the device ESD failure threshold using the voltage steps shown intable 1020-I, as a minimum. Finer voltage steps may optionally be used to obtain a more accurate measure of the failurevoltage. Testing may begin at any voltage step, except for devices which have demonstrated healing effects, including thosewith spark gap protection, which shall be started at the lowest step. Examination of known technology family input or outputV/I damage characteristics ( , curve tracer), or other simplified test verification techniques may be used to validate thefailure threshold ( , cumulative damage effects may be eliminated by retesting at the failure voltage step using a newsample of devices and possibly passing the step).METHOD new sample of devices shall be selected and subjected to the next lower voltage step used. Each device shall be testedMIL-STD-750Dusing three positive and three negative pulses using each of the pin combinations shown in table 1020-II. A minimum ofone-second delay shall separate the sample devices shall be electrically tested to group A, subgroup II applicable (room temperature dc parameters). one or more of the devices fail, the testing of and shall be repeated at the next lower voltage step none of the devices fail, record the failure threshold determined in Note the highest step passed, and use it to classifythe device according to table 1020-II. Junction polarities for ESD conditions typeJunction/polarityBipolar transistor (NPN)Bipolar transistor (PNP)Junction FET's (N-channel)Junction FET's (P-channel)MOSFET's (N- or P-channel)Gate protected FET's (P-channel)Rectifiers (include hot carrier and schottky)ThyristorsUnijunctionsDarlingtonsSmall signal diodesE+ to B-E- to B+G+ to S-G- to S+G to S (both polarities)G to S (both polarities)A- to K+G to K (both polarities)G to B1 (both polarities)E to B (both polarities)A to K (both polarities) Pin combinations to be table 1020-II, select the terminal to be used for the ESD 1020-III. Device ESD failure threshold 1 0 volt to 1,999 voltsClass 22,000 volts to 3,999 voltsClass 34,000 volts to 15,999 voltsNonsensitive Above 15,999 Classification which fail the post test electrical at +25qC of group A, subgroup 2 of the detail specification shall beconsidered class 1 devices subjected to this test shall be considered destroyed and shall not be shipped for use in any 4. Summary. The following details shall be specified in the applicable purchase order or contract, if other than specified test additional or substitute pin combinations, if size, if other than three = 106 : to 107 :C1 = 100 pF 10 percent (Insulation resistance 1012 : minimum)R2 = 1,500 : 1 percentS1 = High voltage relay (Bounceless, mercury wetted, or equivalentS2 = Normally closed switch(Open during discharge pulse and capacitance measurement) performance of this simulator circuit is strongly influenced by parasitics. Capacitances across relays andresistor terminals, and series inductance in wiring and in all components shall be a precaution against transients upon recharge of C1, the supply voltage VS may be reduced before switch S1 isreturned to the charging DUT sockets is not permitted during verification or classification terminals A and B internal to the simulator to obtain opposite polarity is not represents the effective capacitance (see ). current probe connection shall be made with double shielded cable into a 50 : termination at the cable length shall not exceed 3 1020-1. ESD classification test circuit (human body model).METHOD current waveforms shown shall be measured as described in the waveform verification procedure of , usingequipment meeting the requirements of current pulse shall have the following characteristics:tri (rise time) - - - - - - -Less than 10 (delay time) - - - - - -150 20 (peak current) - - - - -Within 10 percent of the IP value shown intable 1020-II for the voltage step (ringing) - - - - - - - -The decay shall be smooth, with ringing, breakpoints, double time constants, or discontinuitiesless than 15 percent Ip maximum, but notobservable 100 ns after start of the 1020-2. ESD classification test circuit waveforms (human body model).METHOD RESISTANCE1. Purpose. The moisture resistance test is performed for the purpose of evaluating, in an accelerated manner, the resistance ofcomponent parts and constituent materials to the deteriorative effects of the high-humidity and heat conditions typical of tropicalenvironments. Most tropical degradation results directly or indirectly from absorption of moisture vapor and films by vulnerable insulatingmaterials, and from surface wetting of metals and insulation. These phenomena produce many types of deterioration, including corrosionof metals; constituents of materials; and detrimental changes in electrical properties. This test differs from the steady-state humidity testand derives its added effectiveness in its employment of temperature cycling, which provides alternate periods of condensation and dryingessential to the development of the corrosion processes and, in addition, produces a "breathing" action of moisture into partially sealedcontainers. Increased effectiveness is also obtained by use of a higher temperature, which intensifies the effects of humidity. The testincludes a low-temperature subcycle that acts as an accelerator to reveal otherwise indiscernible evidences of deterioration sincestresses caused by freezing moisture tend to widen cracks and fissures. As a result, the deterioration can be detected by themeasurement of electrical characteristics (including such tests as voltage breakdown and insulation resistance) or by performance of atest for sealing. Provision is made for the application of a polarizing voltage across insulation to investigate the possibility of electrolysis,which can promote eventual dielectric breakdown. This test also provides for electrical loading of certain components, if desired, in orderto determine the resistance of current-carrying components, especially fine wires and contacts, to electrochemical corrosion. Resultsobtained with this test are reproducible and have been confirmed by investigations of field failures. This test has proved reliable forindicating those parts which are unsuited for tropical field Apparatus. The apparatus used for the moisture resistance test shall include temperature-humidity chambers capable ofmaintaining the cycles and tolerance described on figure 1021-1 and electrical test equipment capable of performing the measurementsin and Procedure. Specimens shall be tested in accordance with through inclusive, and figure 1021-1. Specimens shall bemounted in a manner that will expose them to the test Initial conditioning. Unless otherwise specified and prior to mounting specimens for the moisture resistance test, the device leadsshall be subjected to a bending stress, initial conditioning in accordance with test condition E of method 2036. Where the specificsample devices being subjected to the moisture resistance test have already been subjected to the required initial conditioning, as part ofanother test employing the same sample devices, the lead bend need not be Initial measurements. Prior to step 1 of the first cycle, the specified initial measurements shall be made at room ambientconditions, or as specified. When specified, the initial conditioning in a dry oven (see figure 1021-1) shall precede initial measurementsand the initial measurements shall be completed within 8 hours after removal from the drying Number of cycles. Specimens shall be subjected to 10 continuous cycles, each as shown on figure 1021-1. In the event of nomore than one unintentional test interruption (power interruption or equipment failure) prior to the completion of the specified number ofcycles (except for the last cycle) the cycle shall be repeated and the test may continue. Unintentional interruptions occurring during thelast cycle require a repeat of the cycle plus an additional uninterrupted cycle. Any intentional interruption, or any unintentional interruptionof greater than 24 hours requires completion of missing cycles plus one additional of Subcycle of step 7. During at least 5 of the 10 cycles, a low temperature subcycle shall be performed. At least 1 hour but notmore than 4 hours after step 7 begins, the specimens shall be either removed from the humidity chamber, or the temperature of thechamber shall be reduced, for performance of the subcycle. Specimens during the subcycle shall be conditioned at -10qC +2qC, -5qC,with humidity not controlled, for 3 hours minimum as indicated on figure 1021-1. When a separate cold chamber is not used, care shouldbe taken to assure that the specimens are held at -10qC +2qC, -5qC for the full period. After the subcycle, the specimens shall bereturned to +25qC at 80 percent RH minimum and kept there until the next cycle Applied voltage. During the moisture resistance test as specified on figure 1021-1, when specified (see 4), the device shall bebiased in accordance with the specified bias configuration which should be chosen to maximize the voltage differential between chipmetallization runs or external terminals, minimize power dissipation and to utilize as many terminals as possible to enhance test Conditions (see figure 1021-1). The rate of change of temperature in the chamber is unspecified; however, specimens shall notbe subject to the radiant heat from the chamber conditioning processes. Unless otherwise specified, the circulation of air in the chambershall be at a minimum cubic rate per minute equivalent to five times the volume of the chamber. The steady-state temperature toleranceis r2qC of the specified temperature at all points within the immediate vicinity of the specimens and at the chamber surfaces. Specimensweighing 25 pounds or less shall be transferred between temperature chambers in less than 2 Final measurements. Following step 6 of the final cycle (or step 7 if the subcycle of is performed during the tenth cycle),devices shall be conditioned for 24 hours at room ambient conditions after which either an insulation resistance test in accordance withmethod 1016, or the specified +25qC electrical end-point measurements shall be performed. Electrical measurements may be madeduring the 24 hour conditioning period. However, any failures resulting from this testing shall be counted, and any retesting of thesefailures later in the 24 hour period for the purpose of obtaining an acceptable result is prohibited. No other test ( , seal) shall beperformed during the 24 hour conditioning period. The insulation resistance test or the alternative +25qC electrical end-pointmeasurements shall be completed within 48 hours after removing the devices from the chamber. When the insulation resistance test isperformed, the measured resistance shall be no less than 10 M: and the test shall be recorded and data submitted as part of theend-point data. If the package case is electrically connected to the die substrate by design, the insulation resistance test shall be omittedand the specified +25qC electrical end-point measurements shall be completed within 48 hours after removal of the device from thechamber. A visual examination and any other specified end-point electrical parameter measurements (see ) shall also be Failure criteria. No device shall be acceptable that markings which are missing in whole or in part, faded, smeared, blurred, shifted, or dislodged to the extent that theyare not legible. This examination shall be conducted with normal room lighting and with a magnification of 1X to of corrosion over more than five percent of the area of the finish or base metal of any package element ( , lid, lead,or cap) or any corrosion that completely crosses the element when viewed with a magnification of 10X to missing, broken, or partially formations which bridge between leads or between leads and metal end-point or insulation resistance test :The finish shall include the package and entire exposed lead area from meniscus to the lead tip (excluding the sheared off tipitself) and all other exposed metal Summary. The following details shall be specified in the applicable acquisition measurements and conditions, if other than room ambient (see ). voltage, when applicable (see ), and bias configuration, when required. This bias configuration shall be chosen inaccordance with the following guidelines:(1)Only one supply voltage (V) either positive or negative is required, and an electrical ground (GND) or common magnitude of V will be the maximum such that the specified absolute maximum ratings are not exceeded and testconditions are optimized.(2)Unless otherwise specified, all normally specified voltage terminals and ground leads shall be connected to GND.(3)Unless otherwise specified, all data inputs shall be connected to V. The polarity and magnitude of V is chosen tominimize internal power dissipation and current flow into the device. Unless otherwise specified, all extender inputsshall be connected to GND.(4)All additional leads ( clock, set, reset, outputs) considered individually, shall be connected to V or GND, whicheverminimizes current flow.(5)Leads with no internal connection shall be biased to V or GND whichever is opposite to an adjacent measurements (see ). Final measurements shall include all electrical characteristics and parameters which arespecified as end-point electrical of cycles, if other than 10 (see ). in dry oven before initial measurements, if required (see ).METHOD NOTE: The subcycle of step 7 (See ) shall be performed for a minimum of 5 of the 10 cycles. Humidity is uncontrolled for the -10qC portion of step 1021-1. Graphical representation of moisture-resistance TO SOLVENTS1. Purpose. The purpose of this test is to verify that the markings will not become illegible on the component parts when subjected tosolvents. The solvents will not cause deleterious, mechanical or electrical damage, or deterioration of the materials or Formulation of solvents. The formulation of solvents herein is considered typical and representative of the desired stringency asfar as the usual coatings and markings are concerned. Many available solvents which could be used are either not sufficiently active, toostringent, or even dangerous to humans when in direct contact or when the fumes are Check for conflicts. When this test is referenced, care should be exercised to assure that conflicting requirements, as far as theproperties of the specified finishes and markings are concerned, are not Solvent solutions. The solvent solutions used in this test shall consist of the mixture consisting of the following:(1)One part by volume of isopropyl alcohol, (American Chemical Society) Reagent Grade, or isopropyl alcohol inaccordance with TT-I-735, grade A or B, and(2)Three parts by volume of mineral spirits in accordance with TT-T-291, type II, grade A, or three parts by volume of amixture of 80 percent by volume of kerosene and 20 percent by volume semiaqueous based solvent (defluxer ( , a turpene)) consisting of a minimum of 60 percent Limonene and a surfactantheated to +32 C 5 C. 1 +63 C to +70 C, a mixture consisting of the following: 2/(1)42 parts by volume of deionized water.(2)1 part by volume of propylene glycol monomethyl ether.(3)1 part by volume of Solvent solutions, safety aspects. Solvent solutions listed in a. through d. above exhibit some potential for health and safetyhazards. The following safety precautions should be contact with prolonged contact with adequate open contact with very hot any equivalent EPA approved HCFC or terpene solvent or demonstrated safety precaution for handling this solution ( , same as those for diluted ammonium hydroxide) based rules for of Vessel. The vessel shall be a container made of inert material, and of sufficient size to permit complete immersion of thespecimens in the solvent solutions specified in Brush. The brush shall be a toothbrush with a handle made of a nonreactive material. The brush shall have three long rows ofhard bristles, the free ends of which shall lie substantially in the same plane. The toothbrush shall be used exclusively with a singlesolvent and when there is any evidence of softening, bending, wear, or loss of bristles, it shall be Procedure. The specimens subjected to this test shall be divided into three groups. Metal lidded leadless chip carrier (LCC)packages shall be preconditioned by immersing the specimens in room temperature RMA flux (in accordance with MIL-F-14256, flux,soldering, liquid, rosin base) for 5 to 10 seconds. The specimens shall then be subjected to an ambient temperature of +215 C 5 C for60 seconds +5, -0 seconds. After the preconditioning, each device lid shall be cleaned with isopropyl alcohol. Each group shall beindividually subjected to one of the following first group shall be subjected to the solvent solution as specified in maintained at a temperature of +25 C 5 second group shall be subjected to the solvent solution as specified in maintained at a temperature of+32 C 5 third group shall be subjected to the solvent solution as specified in maintained at a temperature of+63 C to +70 specimens and the bristle portion of the brush shall be completely immersed for 1 minute minimum in the specified solutioncontained in the vessel specified in Immediately following immersion, the specimen shall be brushed with normal hand pressure(approximately 2 to 3 ounces) for 10 strokes on the portion of the specimen where marking has been applied, with the brush specified Immediately after brushing, the above procedure shall be repeated two additional times, for a total of three immersions followed bybrushings. The brush stroke shall be directed in a forward direction, across the surface of the specimen being tested. After completionof the third immersion and brushing, devices shall be rinsed and all surfaces air blown dry. After 5 minutes, the specimens shall beexamined to determine the extent, if any, of deterioration that was Optional procedure for the third group. The test specimens shall be located on a test surface of known area which is located 6 1inches ( centimeters) below a spray nozzle(s) which discharges gpm ( . liters/ minute) of solution (see ) 1in2 ( square centimeters) of surface area at a pressure of 20 5 psi ( kilopascal). The specimens shall be subjected tothis spray for a period of 10 minutes minimum. Within five minutes after removal of the specimens, they shall be examined in accordancewith The specimens may be rinsed with clear water and air blown dried prior to Failure criteria. After subject to the test, evidence of damage to the device and any specified markings which are missing inwhole or in part, faded, smeared, blurred, or shifted (dislodged) to the extent that they cannot be readily identified from a distance of atleast 6 inches ( cm) with normal room lighting and without the aid of magnification or with a viewer having a magnification no greaterthan 3X shall constitute a Summary. The number of specimens to be tested shall be specified in the individual specification (see 3.).METHOD OPERATION LIFE1. Purpose. The purpose of this test is to determine compliance with the specified lambda (O) for devices subjected to the Procedure. The semiconductor device shall be subjected to the steady-state operation life test at the temperature specified for thetime period in accordance with the life test requirements of MIL-S-19500 and herein. The device shall be operated under the otherwise specified, lead-mounted devices should be mounted by the leads with jig mounting clips at least .375 inch ( mm)from the body or from the lead tubulation if the lead tubulation projects from the body. Unless otherwise specified, mounting andconnections to surface mount devices shall be made only at their terminations. Unless a free-air life test is specified, case mounteddevice types ( , stud, flange, disc) shall be mounted by their normal case surface. The point of connection shall be maintained at atemperature not less than the specified the termination of the test, or in accordance with the period specified in MIL-S-19500 and the detail specification, if otherwisedefined, the sample units shall be removed from the specified test conditions and allowed to reach standard test conditions. Specifiedend-point measurements for qualification and quality conformance inspection shall be completed within 96 hours after removal of sampleunits from the specified test conditions. Additional readings may be taken at the discretion of the manufacturer. If end-pointmeasurements cannot be performed within the specified time, the devices shall be subjected to the same test conditions for a minimum of24 additional hours before post test measurements are Summary. The following conditions shall be specified in the detail type and details; rectifying or forward dc current and Vr for rectifiers and signal diodes, dc power (or current) for zenerdiodes, power (and range of VCE and VDS) for bipolar and FETs (see 2.). temperature, if other than room mounting, if other than that specified (see 2.). measurements (see 2.).METHOD OPERATION LIFE (SAMPLE PLAN)1. Purpose. The purpose of this test is to determine compliance with the specified sample plan for devices subjected to the Procedure. Unless otherwise specified, the semiconductor device shall be subjected to the steady-state operation test at thetemperature specified for 340 hours minimum. The device shall be operated under the specified otherwise specified, lead-mounted devices should be mounted by the leads with jig mounting clips at least .375 inch ( mm)from the body or from the lead tubulation if the lead tubulation projects from the body. Unless otherwise specified, mounting andconnections to surface mount devices shall be made only at their terminations. Unless free-air life test is specified, case mounted devicetypes ( , stud, flange, disc) shall be mounted by their normal case surface. The point of connection shall be maintained at atemperature not less than the specified the termination of the test, or in accordance with the period specified by MIL-S-19500 and the detail specification if otherwisedefined, the sample units shall be removed from the specified test conditions and allowed to reach standard test conditions. Specifiedend-point measurements for qualification and quality conformance inspection shall be completed within 96 hours after removal of sampleunits from the specified test conditions. Additional readings may be taken at the discretion of the manufacturer. If end-pointmeasurements cannot be performed within the specified time, the devices shall be subjected to the same test conditions for a minimum of24 additional hours before post test measurements are Summary. The following conditions shall be specified in the detail type and details; rectifying or forward dc current and Vr for rectifiers and signal diodes, dc power (or current) for zenerdiodes, power (and range of VCE and VDS) for bipolar and FETs (see 2.). temperature, if other than room time, if other than 340 hours (see 2.). mounting, if other than that specified (see 2.). measurements (see 2.).METHOD LIFE (NONOPERATING)1. Purpose. The purpose of this test is to determined compliance with the specified lambda (l) for devices subjected to the Procedure. The device shall be stored under the specified ambient conditions (normally the maximum temperature) for a timeperiod in accordance with the life test requirements of MIL-S-19500. In accordance with the life test period specified by MIL-S-19500, thesample units shall be removed from the specified ambient conditions and allowed to reach standard test conditions. Specified end-pointmeasurements for qualification and quality conformance inspection shall be completed within 96 hours after removal of sample units fromthe specified ambient conditions. If measurements can not be performed within the specified time, the devices shall be subjected to thesame test conditions for a minimum of 24 additional hours before post test measurements are performed. Additional readings may betaken at the discretion of the Visual examination. The markings shall be legible after the test. There shall be no evidence (when examined withoutmagnification) of flaking or pitting of the finish or corrosion that will interfere with the mechanical and electrical application of the Summary. The following conditions shall be specified in the detail conditions (see 2.). measurements (see 2.).METHOD (NONOPERATING) LIFE (SAMPLE PLAN)1. Purpose. The purpose of this test is to determine compliance with the specified sample plan for devices subjected to the Procedure. Unless otherwise specified, the device shall be stored under the specified ambient conditions (normally the maximumtemperature) 340 hours minimum. The sample units shall be removed from the specified ambient conditions and allowed to reachstandard test conditions. Specified end-point measurements for qualification and quality conformance inspection shall be completedwithin 96 hours after removal of sample units from the specified ambient conditions. If measurements cannot be performed within thespecified time, the devices shall be subjected to the same test conditions for a minimum of 24 hours before post test measurements areperformed. Additional readings may be taken at the discretion of the Visual examination. The markings shall be legible after the test. There shall be no evidence (when examined withoutmagnification) of flaking or pitting of the finish or corrosion that will interfere with the mechanical and electrical application of the Summary. The following conditions shall be specified in the detail conditions (see 2.). time, if other than 340 hours (see 2.). point measurements (see 2.).METHOD OPERATION LIFE1. Purpose. The purpose of this test is to determine compliance with the specified lambda (l) for devices subjected to the Procedure. The device shall be subjected intermittently to the specified operating and nonoperating conditions for the time period inaccordance with the life test requirements of MIL-S-19500. The on- and off-periods shall be initiated by sudden, not gradual, applicationor removal of the specified operating conditions. Lead mounted devices should be mounted by the leads with jig mounting clips at inch ( mm) from the body or lead tubulation, if the lead tubulation projects from the body. The point of connection shall bemaintained at a temperature not less than the specified temperature. Within the time interval of 24 hours before to 72 hours aftertermination of the test, in accordance with the life test period specified by MIL-S-19500, the sample units shall be removed from thespecified test conditions and allowed to reach standard test conditions. Specified end-point measurements for qualification and qualityconformance inspection shall be completed within 96 hours after removal of sample units from the specified test conditions. Additionalreadings may be taken at the discretion of the Summary. The following conditions shall be specified in the detail conditions (see 2.). and nonoperating cycles (see 2.). temperature (case or ambient). mounting, if other than that specified (see 2.). point measurements (see 2.).METHOD OPERATION LIFE (SAMPLE PLAN)1. Purpose. The purpose of this test is to determine compliance with the specified numbers of cycles for devices subjected to thespecified conditions. It accelerates the stresses on all bonds and interfaces between the chip and mounting face of devices subjected torepeated turn on and off of equipment and is therefore most appropriate for case mount style ( , stud, flange, and disc) Mounting. Clips or fixtures appropriate for holding the device terminations and reliably conducting the heating current shall be method is intended to allow the case temperature to rise and fall appreciably as the junction is heated and cooled; thus it is notappropriate to use a large heat sink. Lead-mounted devices, when specified, should be mounted by the leads with jig mounting clips atleast .375 inch ( mm) from the body, or from the lead tubulation if it projects from the Procedure. All test samples shall be subjected to the specified number of cycles. When stabilized after initial warm-up cycles, acycle shall consist of an "on" period, when power is applied suddenly, not gradually, to the device for the time necessary to achieve a deltacase temperature (delta is the high minus the low mounting surface temperatures) of +85 C (+60 C for thyristors) +15 C, -5 C, followedby an off period, when the power is suddenly removed, for cooling the case through a similar delta temperature. Auxiliary (forced) coolingis permitted during the off period current shall be used for the power required during the "on" period except, for rectifiers and thyristors, equivalent half sine wave (orfull sine wave for triacs) is permissible. The test power, or current, shall be at least the free air rating. For disc types, where functionalmounting requires heat sinking, it shall be at least 25 percent of the continuous, case referenced, rating. The on time (leaded and axialleaded devices) shall be at least 30 seconds. Unless otherwise specified, for TO3, DO5, and larger devices it shall be at least oneminute. Specified end-point measurements for qualification and quality conformance inspection shall be completed within 96 hours afterremoval of sample units from the specified test conditions. Additional readings may be taken at the discretion of the manufacturer. Ifmeasurements cannot be performed within the specified time, the devices shall be subjected to the same test conditions for a minimum of200 additional cycles before post test measurements are Summary. The following conditions shall be specified in the detail conditions (power or current, see 3.). of operating cycles (see 3.), if other than 2, mounting, if other than that specified (see 2.). measurements (see ).NOTE:Heat sinks are not intended to be used in this test, however, small heat sinks may be used when it is otherwise difficult tocontrol case temperature of test samples, such as with small package types ( , TO39).METHOD (FOR DIODES, RECTIFIERS, AND ZENERS)1. Purpose. This test is performed to eliminate marginal devices or those with defects resulting from manufacturing aberrations thatare evidenced as time and stress dependent failures. Without the burn-in, these defective devices would be expected to result in earlylifetime failures under normal use conditions. It is the intent of this test to operate the semiconductor device at specified conditions toreveal electrical failure modes that are time and stress screens for mobile or temperature activated impurities within (and without) the device's passivation layers. It is equallyeffective on most device types including diodes, rectifiers, zeners, and transient voltage , when properly specified, simulates actual device operation but with accelerated conditions. Some of the elements ofHTRB are combined with screening for die bond integrity. It is effective on some device types including diodes, rectifiers, andzeners7. The conditions used for zeners provide the desired HTRB screen concurrently with the SSOP Mounting. Unless otherwise specified in the detail specification, mounting shall be in accordance with the Test condition A, HTRB. The method of mounting is usually optional for high temperature bias since little power is dissipated inthe device. (Devices with normally high reverse leakage current may be mounted to heat sinks to prevent thermal run-away conditions.) Test condition B, with leads projecting from the body ( , axial) shall be mounted by their leads at least .375 inch ( mm) from thebody or lead otherwise specified, devices designed for case mounting ( , stud, flange, and disc) shall be mounted by the stud orcase according to the design specifications for the package. Care must be exercised to avoid stressing or warping of thepackage. Thermally conductive compounds may optionally be used provided that they are removed afterwards and do notleave a residue on the mount types shall be held by their electrical Procedure. The semiconductor device shall be subjected to the burn-in at the temperature and for the time specified herein or onthe detail specification. Pre-burn-in measurements shall be made as specified. The failure criteria shall be as specified in theappropriate detail specification. If measurements cannot be performed within the specified time, the devices shall be subjected to thesame test conditions for a minimum of 24 additional hours before test measurements are Test condition A, HTRB. Unless otherwise specified, HTRB is performed with the cathode positively biased at an artificiallyelevated temperature for 48 hours minimum. These conditions apply to both rectifiers and to avalanche and zener voltage junctions of rectifiers shall be reverse biased at 50 to 80 percent in accordance with figure 1038-1 of their rated workingpeak reverse voltage; avalanche and zener voltage regulators, when specified, shall be reverse biased at 80 percent of theirminimum avalanche or zener voltages except when voltage exceeds 2,500, see figure 1038-1. The reverse bias shall be a dcbias with less than 20 percent ripple except where rectified (pulsating) dc is permitted. The ambient or case test temperatureshall be as specified (normally +150qC for silicon devices) (see figure 1038-1). the end of the high-temperature test time, as specified, the ambient temperature shall be lowered. The test voltage shall bemaintained on the devices until a case temperature of +30qC r5qC is attained. Testing shall be completed within 24 hoursafter the removal of voltage. After removal of the bias voltage, no other voltage shall be applied to the device before taking thepost HTRB reverse current measurement. Post HTRB measurements shall be taken as of 3MIL-STD-750DUni-directional transient voltage suppressors shall be treated as avalanche and zener voltage regulators for the purposes of transient voltage suppressors shall be treated as two discrete avalanche or zener voltage regulators (when specified) witheach polarity taking turns receiving HTRB and post HTRB testing. Post HTRB testing of one must be completed before reversing thedevice and commencing HTRB with opposite polarity bias voltage. The second polarity may be achieved either electrically or bymechanically reversing the Test condition B, steady-state operating power. Unless otherwise specified, the devices shall be subjected to the maximum ratedtest conditions for a minimum of 96 hours. The test temperature shall be as specified. Unless otherwise specified, post burn-in readingsshall be taken within 96 hours. If ambient temperature is specified, it shall comply with the general requirements for HTRB or burn-in ofthis specification (see ). The following indicates the test conditions to be specified for each of the three types of power burn-in test. Unless otherwise specified, average rectified current, peak reverse voltage, frequency, and temperature(case, junction, or ambient) are as specified in the detail bias test. Unless otherwise specified, forward current and temperature (case or junction) are as specified in thedetail regulator (zener) test. Unless otherwise specified, voltage regulator diode current and temperature (case or junction)are as specified in the slash drawing. At the end of the test time, the power level shall be reduced to five percent of theoperating level. If the ambient is artificially elevated, it shall also be reduced to room temperature. The object is to let thedevices cool down under bias. When the junction or case temperature has stabilized to below +50qC, the bias may beremoved and the devices tested within 96 hours after removal of reverse bias. No other voltage may be applied to the devicesuntil completion of electrical 1038-1. Voltage Summary. The test condition letter (A or B) and the following details shall be specified in the applicable detail Test condition A, temperature (see ). conditions (see and ). time (see ). and post burn-in measurements (see 3. and ). for completion of post burn-in measurements, if other than 24 hours (see ). for failure (see 3.). Test condition B, steady-state operating temperature (see ). conditions (see and ). time if other than 96 hours (see ). and post burn-in measurements (see 3. and ). for completion of post burn-in measurements, if other than 96 hours (see ). for failure (see 3.).METHOD (FOR TRANSISTORS)1. Purpose. This test is performed to eliminate marginal devices or those with defects resulting from manufacturing aberrations thatare evidenced as time and stress dependent failures. Without the burn-in, these defective devices would be expected to result in earlylifetime failures under normal use conditions. It is the intent of this test to operate the semiconductor device at specified conditions toreveal electrical failure modes that are time and stress Procedure. The semiconductor device shall be subjected to the burn-in at the temperature and for the time specified measurements shall be made as applicable. The failure criteria shall be as Mounting. Devices with leads projecting from the body shall be mounted by their leads at least .250 inch ( mm) from theseating plane. Unless otherwise specified, devices with studs or case shall be mounted by the stud or Test condition A, steady-state reverse bias. The transistor primary blocking junction, as specified, shall be reverse biased for 48hours minimum, except PNP bipolar transistors shall be 24 hours, at the ambient temperature specified (normally +150 C) and at 80percent of its maximum rated collector-base voltage. For bipolar transistors, the VCB base is not to exceed the maximumcollector-emitter voltage rating. For field-effect (signal or low power) transistors, the gate to source voltage, with drain to source shorted,shall be as specified. At the end of the high-temperature test time, specified herein, the ambient temperature shall be lowered. The testvoltage shall be maintained on the devices until TC = +30 C 5 C is attained. After room ambient temperature has been established, thebias voltage shall be removed. After removal of the bias voltage, no other voltage shall be applied to the device before taking the postburn-in reverse-current measurement(s). Unless otherwise specified, after burn-in voltage is removed, post burn-in measurements shallbe completed within 24 hours. If measurements cannot be performed within the specified time, the devices shall be subjected to thesame test conditions for a minimum of 24 additional hours before post test measurements are Test condition B, steady-state power. All devices shall be operated at the maximum rated power related to the test temperaturefor 160 hours minimum at the specified test conditions (excluding microwave). bipolar transistors, the temperature and power shall be specified. Unless otherwise specified, the temperature shall be asfollows:TA = room ambient as defined in the general requirements, herein. for small signal, switching, andmedium power devices intended for printed circuit board mounting; TJ = maximum rated temperature,+0 C, -25 C, for devices intended for chassis or heat sink mounting. Case temperature burn-in atmaximum ratings (typically TC = +100 C) may be substituted on the chassis or heat sink mounteddevices at the supplier's option. If the voltage conditions specified herein cause the SOA rating to beexceeded, then the voltage shall be decreased until the SOA rating is met while maintaining the fullrated power condition. For microwave bipolar transistors, the temperature, voltage, and current shallbe as specified in the detail unijunction and field-effect (signal and low power) transistors, the temperature, voltage, and current shall be as burn-in measurements shall be as otherwise specified, post burn-in readings shall be taken within 96 hours. If measurements cannot be performedwithin the specified time, the devices shall be subjected to the same test conditions for a minimum of 24 additional hoursbefore post test measurements are of 2MIL-STD-750D3. Summary. Test condition letter and the following conditions shall be specified in the detail Test condition to be reverse biased (see ). to source voltage for FETs (see ). temperature (see ). time for FETs (see ). for post burn-in reverse current measurement (see ). for completion of post burn-in measurements, if other than 24 hours (see ). for failure (see 2.). Test condition temperature, if other than as specified in conditions (see ). for bipolar transistors (see ). and current for unijunction and FETs (see ). and post burn-in measurements (see ). for completion of post burn-in measurements, if other than as specified in for failure (see 2.).METHOD 1040BURN-IN (FOR THYRISTORS(CONTROLLED RECTIFIERS))1. Purpose. The purpose of this test is to eliminate marginal or defective semiconductor devices by operating them at specifiedscreening conditions which reveal electrical failure modes that are time and stress dependent. In the absence of burn-in, these defectivedevices would be expected to result in early lifetime failures under normal use Procedure. Lead mounted devices shall be mounted by the leads at least .375 inch ( mm) from the body or lead tubulation, if thelead tubulation projects from the body. Unless otherwise specified, stud or case mounted devices shall be mounted by the stud or caserespectively. The devices shall then be subjected to the burn-in screen(s) at the temperature and for the time specified. Preburn-in andpost burn-in measurements shall be made as Test condition A (ac blocking voltage). The rated peak reverse and the rated peak forward blocking voltage shall be alternatelyapplied, each in the form of a 60 Hz half wave sinusoidal pulse using the circuit of figure 1040-1. The test temperature shall be asspecified. At the end of the specified high temperature test time, the ambient temperature shall be lowered. The test voltage shall bemaintained on the devices until TC = +30 C 5 C is attained. After bias is removed and prior to post test measurements, the devicesshall be maintained at room ambient temperature and no voltage shall be applied prior to that voltage specified for the post testmeasurements. The post test end points shall be completed within the specified time after the bias voltage is removed. Any device whichswitches from the off-state to the on-state as indicated by a blown fuse shall be removed from the 1040-1. AC blocking voltage Test condition B (dc forward blocking voltage). The rated dc forward blocking voltage shall be applied as indicated in the circuit onfigure 1040-2. The test temperature shall be as specified. At the end of the specified high-temperature test time, the ambienttemperature shall be lowered. The test voltage shall be maintained on the devices until TC = +30 C 5 C is attained. After bias isremoved and prior to post test measurements, the devices shall be maintained at room ambient temperature and no voltage shall beapplied prior to that voltage specified for the post test measurements. The post test end points shall be completed within the specifiedtime after the bias voltage is removed. Any device which switches from the off-state to the on-state as indicated by a blown fuse shall beremoved from the Measurements. Initial readings shall be taken prior to burn-in. Post-test readings shall be taken within 96 10401 of 2MIL-STD-750DFIGURE 1040-2. DC forward blocking voltage Summary. The test condition letter and the following conditions shall be specified in the detail condition forward and reverse blocking voltage (see ). temperature (see ). of burn-in (see ). (see figure 1040-1). and post burn-in measurements (see 3.). condition forward blocking voltage (see ). temperature (see ). of burn-in (see ). (see figure 1040-2). and post burn-in measurements (see 3.).METHOD 10402MIL-STD-750DMETHOD ATMOSPHERE (CORROSION)1. Purpose. This test is an accelerated laboratory corrosion test simulating the effects of seacoast atmospheres on Apparatus. Apparatus used in the salt-atmosphere test shall include the chamber with racks for supporting for atomizing the salt solution, including suitable nozzles and compressed-air means and for humidifying the air at a temperature above the chamber Procedure. The device shall be placed within the test chamber. Unless otherwise specified, a salt atmosphere fog having atemperature of +35 C (+95 F) shall be passed through the chamber for a period of 24 +2, -0 hours. The fog concentration and velocityshall be adjusted so that the rate of salt deposit in the test area is between 10 and 50 g/m2 Examinations. Unless otherwise specified, upon completion of the test, and to aid in the examinations, devices shall be prepared inthe following manner: Salt deposits shall be removed by a gentle wash or dip in running water not warmer than +37 C (+100 F) and alight brushing, using a soft-hair brush or plastic bristle brush. A device with illegible markings, leads missing, broken, or partiallyseparated, evidence (when examined with 10X magnification) of flaking or pitting of the finish or corrosion exceeding five percent of thepackage area or five percent of the lead shall be considered a failure. Discoloration of the plating or lead finish shall not be considered afailure. The marking legibility requirement shall not apply to characters with a height of less than .030 inches ( mm).5. Summary. The following conditions shall be specified in the detail of exposure, if other than that specified (see 3.). and examinations after test (see 4.).METHOD AND LIFE TEST FOR POWER MOSFET's ORINSULATED GATE BIPOLAR TRANSISTORS (IGBT)1. Purpose. Test conditions A, B, and C are performed to eliminate marginal devices or those with defects resulting frommanufacturing aberrations that are evidenced as time and stress failures under normal use conditions. Test condition D is performed toeliminate marginal lots with manufacturing defects. For the IGBT, replace the drain and source MOSFET designations with collector andemitter IGBT designations,D = C and S = Procedure. The semiconductor device shall be subjected to the burn-in at the temperature and for the time specified measurements shall be made as applicable. The failure criteria shall be as Test condition A, steady-state reverse bias. All devices shall be operated at 80 percent of the maximum rated drain to sourcevoltage at the specified test temperature for 160 hours minimum, at the specified test conditions. The drain to source voltage, with gate tosource shorted, shall be as specified. At the end of the high-temperature test time, specified herein, the ambient temperature shall belowered. The burn-in voltage shall be maintained on the devices until TC = 30 C 5 C is attained. The interruption of bias for up to oneminute for the purpose of moving devices to cool down positions separate from the chamber within which life testing was performed shallnot be considered removal of removal of the burn-in voltage, no other voltage shall be applied to the device before taking the post burn-in reverse currentmeasurement(s). After burn-in voltage is removed, post burn-in measurements shall be completed within 96 hours, unless otherwisespecified. (See figure 1042-1.) Unless otherwise specified, the burn-in temperature shall be TA = 150 C. The VDS burn-in voltage shallbe as follows. For IGBT devices, burn-in temperature shall be TJ = 150 C, -15 C to +0 C, and test time shall be 96 hours minimum. If V(BR)DSS is 20 V VDS shall be 16 V 30 V 24 V 40 V 32 V 60 V 48 V 80 V 64 V 90 V 72 V 100 V 80 V 120 V 96 V 150 V 120 V 170 V 136 V 200 V 160 V 240 V 192 V 350 V 280 V 400 V 320 V 450 V 360 V 500 V 400 V 600 V 480 VV(BR)DSS voltages in between shall revert to the next lower VDS burn-in Temperature accelerated test details. In an accelerated test devices are subjected to bias conditions at a temperatureexceeding the maximum rated junction temperature. The maximum ambient temperature for MOSFETs is +175 C for a minimum of 48hours. It is recommended that an adequate sample of devices be exposed to the high temperature while measuring the voltage(s) andcurrent(s) of the devices to assure that the applied stresses do not induce damaging overstress. An adequate sample which hascompleted the accelerated test should also be subjected to a 1,000 hour steady state reverse bias at standard test conditions to assurethe devices have not been deleteriously affected. Details of the accelerated test will be found in the detail and/or general of Test condition B, steady-state gate bias. All devices shall be operated at 80 percent of the maximum rated gate to source voltageat the specified temperature for a minimum of 48 hours. (See figure 1042-2.) For MOS power transistors, the temperature and voltageshall be as specified. Unless otherwise specified, the temperature (TA) shall be 150 C. If maximum rated VGS is 10 V Burn-in voltage (VGS) shall be 8 V 15 V 12 V 20 V 16 V 30 V 24 V 40 V 32 VVGS voltages in between shall revert to the next lower Test condition C, steady-state power. All devices shall be operated at the maximum junction temperature +0 C, 24 C by meansof applying power to the device while maintaining an ambient temperature of +25 C +10 C, -5 C. The junction temperature shall beverified by means of measuring junction temperature using the change in body diode voltage drop or calculated by applying the followingequations:TJ = R4JA x PD + TA Not heat sink used orTJ = R4JC x PD + TC Heat sink usedTC = Temperature of caseTA = Ambient air temperatureTS = Temperature of heat sinkPD = VDS x IDVDS = Drain-source voltageID = Drain-source currentNote: The power indicated by the safe operating curve shall not be Test condition D, intermittent power. 1/ All devices shall be subjected to the number of cycles as specified. A cycle shallconsist of applying power to the device for the time necessary to achieve a +100 C +15 C, -10 C minimum rise in junction temperaturefollowed by an off period for the time necessary for the junction to cool. Forced air cooling is permitted during the off period power level, power-on time, and heat sink used, if any, shall be chosen to ensure that at the end of the heating cycle, the casetemperature is not more than 15 C below the junction temperature. The rise in junction temperature during the on period shall be verifiedby means of measuring junction temperature using the change in body diode voltage drop or calculated by applying the followingequations.'TJ = PT R4JA (1 - Exp - t/Tp) where PT = VDS IDTP = thermal time constant of device package, and the heat sink = heating time, R4JA = thermal resistance junction to ambient, for the period of heating time specified, of the device and any necessary heat sink test is intended to allow the case temperature to rise and fall appreciably as the junction is heated andcooled; thus, it is not appropriate to use a large heat sink or a high power short This test condition is 3. Summary. Test condition letter and the following details shall be specified in the individual Test condition Drain to source voltage for MOS power field-effect transistors (VDS) (see ).b. Test temperature, if other than specified in Test time, if other than specified in Voltage for post burn-in reverse current measurement (see ).e. Criteria for Test condition Test temperature, if other than as specified in Test conditions (see ).c. Voltage for MOS power field-effect transistors (see ).d. Preburn-in and post burn-in Criteria for Test condition Ambient temperature and thermal resistance (see ).b. Voltage and current, if other than specified in Preburn-in and post burn-in Total test time (see ).e. Criteria for Test condition Ambient temperature (if one is desired) and thermal resistance (see ).b. Voltage and current, if other than specified in Pretest and post test Number of cycles (see ).e. Criteria for Minimum heating : 1. The load circuit shall be selected or designed to ensure that the voltage across the load circuit of each acceptable device shall not exceed 10 percent of the specified test voltage. The load circuit may be a resistor, fuse, or circuit which: a. Protects the power supply. b. Isolates the defective devices from the other devices under test. c. Insures a minimum of 98 percent of the specified test voltage is applied across the DUT. 2. If the circuit does not maintain bias on a failed device, then means must be provided to identify that 1042-1. High temperature reverse bias test 1042-2. High temperature gate bias SPRAY (CORROSION)1. Purpose. This test is proposed as an accelerated laboratory corrosion test simulating the effects of seacoast atmosphere ondevices. This test can also be used to detect the presence of free iron contaminating the surface of another metal, by inspection of thecorrosion Apparatus. Apparatus used in the salt-spray test shall include the chamber with racks for supporting reservoir with means for monitoring an adequate level of for atomizing the salt solution, including suitable nozzles and compressed-air means and for humidifying the air at a temperature above the chamber Chamber. The chamber and all accessories shall be made of material which will not affect the corrosiveness of the fog, such asglass, hard rubber, or plastic. Wood or plywood should not be used because they are resiniferous. Materials should not be used if theycontain formaldehyde or phenol in their composition. In addition, all parts which come in contact with test specimens shall be of materialsthat will not cause electrolytic corrosion. The chamber and accessories shall be so constructed and arranged that there is no directimpinging of the spray or dripping of the condensate on the specimens, so that the spray circulates freely about all specimens to thesame degree, and so that no liquid which has come in contact with the test specimens returns to the salt-solution reservoir. The chambershall be properly vented to prevent pressure build up and allow uniform distribution of salt spray. The discharge end of the vent shall beprotected from strong drafts which can cause strong air current in the Atomizers. The atomizer of atomizers used shall be of such design and construction as to produce a finely divided, wet dense nozzle shall be made of material which does not react with the salt Air supply. The compressed air entering the atomizers shall be free from all impurities such as oil and dirt. Means shall beprovided to humidify and warm the compressed air as required to meet the operating conditions. The air pressure shall be suitable toproduce a finely divided dense fog with the atomizer or atomizers used. To insure against clogging the atomizers by salt deposition, theair should have a relative humidity of 95 to 98 percent at the point of release from the nozzle. A satisfactory method is to pass the air invery fine bubbles through a tower containing heated water. The temperature of the water should be +95qF (+35qC) and often higher. Thepermissible temperature increased with increasing volume of air and with decreasing heat insulation of the chamber and temperature ofits surroundings. It should not exceed a value above which an excess of moisture is introduced into the chamber (for example, +110qF(+ ) at an air pressure of 12 pounds per square inch), or a value which makes it impossible to meet the requirement for Salt solution. The salt-solution concentration shall be 5 percent by weight. The salt used shall be sodium chloride containing onthe dry basis of more than percent of sodium iodide, and not more than percent of total impurities. The 5-percent solution shall beprepared by dissolving 5 r1 parts by weight of salt in 95 parts by weight of distilled or other water. Distilled or other water used in thepreparation of solutions shall contain nor more than 200 parts per million of total solids. The solution shall be kept free from solids byfiltration using a filter similar to that shown on figure 1046-1, and located in the salt solution reservoir in a manner such as that illustratedon figure 1046-2. The solution shall be adjusted to and maintained at a specific gravity in accordance with figure 1046-3. The pH shallbe maintained between and when measured at temperature between +93qF and +97qF (+ and + ). Only dilute cpgrade hydrochloric acid or sodium hydroxide shall be used to adjust the pH. The pH measurement shall be made electrometrically usinga glass electrode with a saturated potassium-chloride bridge or by a colorimetric method such as bromothymol blue, provided the resultsare equivalent to those obtained with the electrometric Filter. A filter fabricated of noncorrosive materials similar to that shown on figure 1046-1 shall be provided in the supply line andimmersed in the reservoir in a manner such as shown on figure of Preparation of specimens. Specimens shall be given a minimum of handling, particularly on the significant surfaces, and shall beprepared for test immediately before exposure. Unless otherwise specified, uncoated metallic or metallic-coated specimens shall bethoroughly cleaned of oil, dirt, and grease as necessary until the surface is free from water break. The cleaning methods shall not includethe use of corrosive solvents nor solvents which deposit wither corrosive or protective films, nor the use of abrasives other than a paste ofpure magnesium oxide. Specimens having an organic coating shall not be solvent cleaned. Those portions of specimens which comesin contact with the support and, unless otherwise specified in the case of coated specimens or samples, cut edges and surfaces notrequired to be coated, shall be protected with a suitable coating of wax or similar substance impervious to Procedure. The following exceptions shall the conclusion of the test, the device will be dried for 24 hours at +40qC r5qC before the examination. A device withillegible marking, evidence (when examined without magnification) of flaking or pitting of the finish or corrosion that willinterfere with the application of the device shall be considered a otherwise specified, salt solution shall be 20 percent by Location of specimens. Unless otherwise specified, flat specimens and, where practicable, other specimens shall be supported insuch a position that the significant surface is approximately 15q from the vertical and parallel to the principal direction of horizontal flow ofthe fog through the chamber. Other specimens shall be positioned so as to insure most uniform exposure. Whenever practicable, thespecimens shall be supported from the bottom or from the side. When specimens are suspended from the top, suspension shall be bymeans of glass or plastic hooks or wax string; if plastic hooks are used, they shall be fabricated of material which is nonreactive to the saltsolution such as Lucite. The used of metal hooks is not permitted. Specimens shall be positioned so that they do not contact each other,so that they do not shield each other from the freely settling fog, and so that corrosion products and condensate from one specimen donot fall upon Operating Temperature. The test shall be conducted with a temperature in the exposure zone maintained at +95qF +2qF, -3qF (+35qC+ , ). Satisfactory methods for controlling the temperature accurately are by housing the apparatus in a properly controlledconstant-temperature room, by thoroughly insulating the apparatus and preheating the air to the proper temperature prior to atomization,and by jacketing the apparatus and controlling the temperature of the water or of the air used. The use of immersion heaters for thepurpose of maintaining the temperature within the chamber is Atomization. The conditions maintained in all parts of the exposure zone shall be such that a suitable receptacle placed at anypoint in the exposure zone will collect from to milliliters of solution per hour for each 80 square centimeters of horizontal collectingarea (10 centimeters diameter) based on an average run of at least 16 hours. The 5-percent solution thus collected shall have a sodium-chloride content of from 4 to 6 percent (specific gravity) in accordance with figure 1046-3 when measured at a temperature between+93qF and +97qF (+ and + ). At least two clean fog-collecting receptacles shall be used, one placed near any nozzle andone placed as far as possible from all nozzles. Receptacles shall be fastened so that they are no shielded by specimens and so that nodrops of solution from specimens or other sources will be collected. The specific gravity and quantity of the solution collected shall bechecked following each salt-spay test. Suitable atomization has been obtained in boxes having a volume of less than 12 cubic feet withthe following pressure of from 12 to 18 pounds per square of from to inch in of approximately 3 quarts of the salt solution per 10 cubic feet of box volume per 24 using large-size boxes having a volume considerably in excess of 12 cubic feet, the above conditions may have to be modified inorder to meet the requirements for operating Length of test. The length of the salt-spray test shall be that indicated in one of the following test conditions, as specified: Test condition Length of test A - - - - - - - - 96 hours B - - - - - - - - 48 hoursUnless otherwise specified, the test shall be run continuously for the time indicated or until definite indication of failure is observed, withno interruption except for adjustment of the apparatus and inspection of the Measurements. At the completion of the exposure period, measurements shall be made as specified. To aid in examination,specimens shall be prepared in the following manner, unless otherwise specified: Salt deposits shall be removed by a gentle wash or dipin running water not warmer than +100qF (+ ) and a light brushing, using a soft-hair brush or plastic-bristle Summary. The following details are to be specified in the individual mounting and details, if applicable (see ) condition letter (see ) after exposure (see 4).METHOD Inches | Millimeters | | | | | 1046-1. Salt solution 1046-2. Location of salt solution 1046-3. Variations of specific gravity of salt (NaCl) solution with 1048BLOCKING LIFE1. Purpose. The purpose of this test is to determine compliance with the specified lambda for devices subjected to the Mounting. The method of mounting is usually optional for blocking life tests since little power is dissipated in the device. (Deviceswith normally high reverse leakage current may be mounted to heat sinks to prevent thermal run-away conditions.)3. Procedure. Blocking life is performed with the primary blocking junction, or insulation, reverse biased at an artificially elevatedtemperature for the time period in accordance with the life test requirements of MIL-S-19500 and herein; at the temperature specified(normally +150 C and at 80 to 85 percent of the rated voltage relevant to the device (VR, VZ(min), VCB, VAG, VDG, and VGS).At the end of the high-temperature test time, as specified, the ambient temperature shall be lowered. The test voltage shall be maintainedon the devices until a case temperature of +30 C 5 C is attained. After this ambient temperature has been established, the bias voltageshall be maintained until testing is performed; testing shall be completed within 24 hours after the removal of power. After removal of thebias voltage, no other voltage shall be applied to the device before taking the post test leakage current measurement. Post testmeasurements shall be taken as Summary. The following details shall be specified in the applicable detail temperature (see 3.). conditions: Voltage and terminals to be biased (see 2. and 3.). time (see 3.). and post test measurements (see 3.). for completion of post test measurements, if other than 24 10481/2MIL-STD-750DMETHOD CYCLING (AIR TO AIR)1. Purpose. This test is conducted to determine the resistance of a part to extremes of high and low temperatures, and to the effect ofalternate exposures to these Terms and Load. The specimens under test and the fixtures holding those specimens during the test. Maximum load shall be determinedby using the worst case load temperature with specific specimen loading. Monolithic loads used to simulate loading may not beappropriate when air circulation is reduced by load configuration. The maximum loading must meet the specified Monitoring sensor. The temperature sensor that is located and calibrated so as to indicate the same temperature as at the worstcase indicator specimen location. The worst case indicator specimen location is identified during the periodic characterization of theworst case load Worst case load temperature. The worst case load temperature is the temperature of a specific area in the chamber whenmeasured by thermocouples located at the center and at each corner of the load. The worst case load temperature shall be determined atperiodic Working zone. The volume in the chamber(s) in which the temperature of the load is controlled within the limits specified in Specimen. The device or individual piece being Transfer time. The elapsed time between specimen removal from one temperature extreme and introduction into the Maximum load. The largest load for which the worst case load temperature meets the timing requirements (see ). Dwell time. The time from introduction of the load into the chamber until the load is transferred out of the Apparatus. The chamber(s) used shall be capable of providing and controlling the specified temperatures in the working zone(s)when the chamber is loaded with a maximum load. The thermal capacity and air circulation must enable the working zone and loads tomeet the specified conditions and timing (see ). Worst case load temperature shall be continually monitored during test by indicatorsor recorders reading the monitoring sensor. Direct heat conduction to specimens shall be Procedure. Specimens shall be placed in such a position with respect to the air stream that there is substantially no obstruction tothe flow of air across and around the specimen. When special mounting is required, it shall be specified. The specimen shall then besubjected to the specified condition for the specified number of cycles performed continuously. This test shall be conducted for aminimum of 20 cycles using test condition C. One cycle consists of steps 1 and 2 or the applicable test condition to be counted as acycle. Completion of the total number of cycles specified for the test may be interrupted for the purpose of test chamber loading orunloading of device lots or as the result of power or equipment failure. However, if for any reason the number of incomplete cyclesexceed 10 percent of the total number of cycles specified, one cycle must be added for each incomplete Timing. The total transfer time from hot to cold or from cold to hot shall not exceed one minute. The load may be transferred whenthe worst case load temperature is within the limits specified in table 1051-I. However, the dwell time shall not be less than 10 minutesand the load shall reach the specified temperature within 15 of 2MIL-STD-750DTABLE 1051-I. Temperature-cycling test conditions. |||||Step |Minutes| Test condition temperature ( C) |||||||||||| | | A | B | C | D | E | F | G |||||||||||| 1| t 10|-55 +0|-55 +0|-55 +0|-65 +0|-65 +0|-65 +0|-55 +0||Cold || -10| -10| -10| -10| -10| -10| -10|| | | | | | | | | |||||||||||| 2| t 10| 85 +10|125 +15|175 +15|200 +15|300 +15|150 +15|150 +15||Hot|| -0| -0| -0| -0| -0| -0| -0|| | | | | | | | | |NOTE: Steps 1 and 2 may be interchanged. The load temperature may exceed the + or - zero (0) tolerance during the recovery time. Other tolerances shall not be Summary. The following details shall be specified in the applicable detail mounting, if applicable (see 3.). condition letter, if other than test condition C (see 3.). of test cycles, if other than 20 cycles (see 3.). measurements and examinations, , end-point electrical measurements, seal test (method 1071), or otheracceptance criteria).METHOD ENVIRONMENT STRESS TEST1. Purpose. The purpose of this test is to determine device design susceptibility to intermittent open failures in conformally coatedcircuit boards environments while under thermal cycle. The destructive effects of tension and compression are magnified in the pottedcondition allowing for early detection of design of three cubic inches minimum with rigid walls of .125 inch ( mm) for testing corrected to a common bussbar arranged in a common cathode or common anode configuration (seefigure 1054-1). cycling plate capable of maintaining +70 tracer, Tektronix 576 or medium, Emerson and Cuming Stycast 2851 MT or devices in a common connection configuration into the container with provisions made to ensure device clearance inch ( mm) minimum from the container 1054-1. Potted stycast potting compound into shell and allow to cure while following all manufacturer's of cured assembly on a hot plate and allow the assembly to reach thermal equilibrium of +70 C. Unless otherwisespecified, observe the forward voltage trace of each device at a current level of 100 mA. Forward voltage trace should showno incidence of instability or open condition. Record all failures by serial assembly to cool at room temperature and place into a thermal shock chamber to perform 20 shocks in accordance withmethod 1051 herein. Remove assembly and allow to reach room and record MISSION TEMPERATURE CYCLE1. Purpose. This test is to determine the ability of devices to withstand the effect of thermal stress and rapid dimensional change oninternal structural elements caused by the application of power in rapidly changing temperature environments as in mission profile Apparatus. The equipment required shall consist of that listed below and shall have the stated chamber of sufficient temperature range and change rate capability with cabling exiting through insulated barriers to externalbias and monitoring electronics. Cabling for all monitoring equipment shall provide Kelvin regulated power supply(s) capable of maintaining the stated bias voltage monitoring device with capability of indicating an open circuit of 20 ms or more in conforming to all electrical and mechanical parameter requirements shall be first subjected to high temperaturestabilization bake of method 1032 herein. They shall then be subjected to non-operational thermal shock of method 1051herein, except that no dwell time is required at +25 C. Test condition "C" shall be +175 C, +5 C, -0 C. Temperature shallremain at the stabilized extremes for 10 minutes measurements shall be performed to ensure that proceeding to the monitored thermal cycle portion of this test alldevices have remained within otherwise specified, the temperature extremes shall be as stated below (from worse case mission profile requirementsof table I in MIL-STD-781). temperature and operating profile shall be specified on figure 1055-1. Temperature change rate shall average not lessthan 5 C per minute, but not greater than 10 C per device(s) shall be placed individually or in series connection within the chamber. The device(s) shall be connected to aconstant current power supply capable of supplying current to raise the device junction(s) to +125 C minimum, +150 Cmaximum temperature during the high temperature portion of each of 3MIL-STD-750DFIGURE 1055-1. Monitored mission Electrical monitoring. Connect electrical monitoring volt meter leads to the extremes of the device(s) and series resistor (see figure1055-2). Apply the current to raise each junction temperature approximately +50 C. The value of R shall be chosen to cause a 10 3percent increase in monitoring voltage, VM, if open circuit occurs. Open switch S1 and verify an increase in VM to verify circuit 1055-2. Monitored mission Monitoring voltage increase. Close S1 and perform six cycles of figure 1055-1 while monitoring for increases in voltage levelabove the highest (cold temperature) Failures. Failures in the first two cycles may be considered non-chargeable de-bug events, if analysis finds fault with test last four cycles shall be failure :Unless otherwise specified, a momentary, or continuous, open circuit (indicated by an increase in the monitored voltage) inany of the last four cycles, shall be considered SHOCK (LIQUID TO LIQUID)1. Purpose. This test is conducted to determine the resistance of the part to sudden exposure to extreme changes in temperature andto the effect of alternate exposures to these Terms and Cycle. A cycle consists of starting at ambient room temperature, proceeding to step 1, then to step 2, or alternately proceedingto step 2, then to step 1, and then back to ambient room temperature without Dwell time. The total time the load is immersed in the Load. The DUTs and the fixtures holding those Maximum load. The maximum mass of devices and fixtures that can be placed in the bath while maintaining specifiedtemperatures and Specimen. The device or individual piece being Transfer time. The elapsed time measured from removal of the load from one bath until insertion in the other Worst case load temperature. The body temperature of a specific device located at the center of the Apparatus. The baths used shall be capable of providing and controlling the specified temperatures in the working zone(s) whenthe bath is loaded with a maximum load. The thermal capacity and liquid circulation must enable the working zone and loads to meet thespecified conditions and timing (see ). Worst case load temperature shall be continually monitored during test by indicators orrecorders reading the monitoring sensor(s). The worst case load temperature under maximum load conditions and configuration shall beverified as needed to validate bath performance. Perfluorocarbons that meet the physical property requirements of table shall beused for conditions B and Procedure. Specimens shall be placed in the bath in a position so that the flow of liquid across and around them is substantiallyunobstructed. The load shall then be subjected to condition A or as otherwise specified (see 4b) of table for a duration of 15cycles. Completion of the total number of cycles specified for the test may be interrupted for the purpose of loading or unloading ofdevice lots or as the result of power or equipment failure. However, if the number of interruptions for any given test exceeds 10 percent ofthe total number of cycles specified, the test must be restarted from the Timing. The total transfer time from hot to cold or from cold to hot shall not exceed 10 seconds. The load may be transferredwhen the worst case load temperature is within the limits specified in table However, the dwell time shall not be less than 2minutes and the load shall reach the specified temperature within 5 Summary. The following details shall be specified in the applicable detail mounting, if condition, if other than test condition B (see 3.). of test cycles, if other than 15 cycles (see 3.). measurements and examinations such as end-point electrical measurements, seal test (method 1071), or otheracceptance criteria).METHOD of 2MIL-STD-750DTABLE Physical property requirements of perfluorocarbon fluids. 1/ |||||| Test condition| B| C| ASTM test|| | | | method ||||| ||| Step 1| Boiling point, C | >125 | >150 | D1120 ||||||||Density at 25 C gm/ml| > | D941|||Dielectric strength| >300| D877||| volts/mil|||||Residue, microgram/gram| <50| D2109|| |Appearance | Clear, colorless liquid | Not applicable |||||||Step 2|Density at 25 C gm/ml| > | D941|||Dielectric strength| >300| D877||| volts/mil|||||Residue, microgram/gram| <50| D2109|| |Appearance | Clear, colorless liquid | Not applicable |1/ The perfluorocarbon used shall have a viscosity less than or equal to the thermal shock equipment manufacturer's recommended viscosity at the minimum Thermal shock temperature tolerances and suggested fluids. 1/ |||||| Test conditions| A and B | C | D ||||||| | Temperature | Temperature | Temperature ||||||||Step 1| Temperature| 100 +10| 125 +10| 150 +10||| tolerance, C | -2 | -0 | -0 ||||||||| Recommended fluid| Water 2/| Perfluoro-| Perfluoro-||||or perfluoro-| carbon 3/| carbon 3/|||| carbon 3/|||| | | | | ||||||||Step 2| Temperature| -0 +2| -55 +0| -65 +0||| tolerance, C | -10 | -10 | -10 ||||||||| Recommended fluid| Water 2/| Perfluoro-| Perfluoro-||||or perfluoro-| carbon 3/| carbon 3/|||| carbon 3/|||| | | | | |1/ Ethylene glycol shall not be used as a thermal shock test Water is indicated as an acceptable fluid for this temperature range. Its suitability chemically shall be established prior to use. When water is used as the fluid of for condition A and the specified temperature tolerances are insufficient due to altitude considerations, the following alternate test conditions may be Temperature: +100 C -6 C, 0 C +6 Cycles shall be increased to Perfluorocarbons contain no chlorine or MEASUREMENT,CASE AND STUD1. Purpose. This proposal covers a method of measuring case temperature of hex-base Test Type of thermocouple. The thermocouple material shall be copper-constantan, as recommended by the "Standard Handbook forElectrical Engineers", for the range of -190 C to +350 C. The wire size shall be no larger than AWG size 30. The junction of thethermocouple shall be welded together to form a bead rather than soldered or Accuracy. The thermocouple shall have an accuracy of .5 C. Under load conditions, slight variations in the temperature ofdifferent points on the case may reduce this accuracy to C for convection cooling, and C for forced air Method of mounting. A small hole, just large enough to insert the thermocouple, shall be drilled approximately .031 inch ( mm)deep into the flat of the case hex at a point chosen by the manufacturer. The edge of the hole should then be peened with a small centerpunch to force a rigid mechanical contact with the welded bead of the thermocouple. If forced air ventilation is used, the thermocoupleshall be mounted away from the air stream and the thermocouple leads close to the junction shall be Other methods of mounting. Other methods of mounting thermocouple, with the possible exception of the thermocouple weldeddirectly to the case, will result in temperature readings lower than the actual temperature. These deviations will result contact with the case using cemented heat sink in contact with the thermocouple using pressure Summary. The following conditions shall be specified in the detail of mounting (see 3.). equipment, if POINT1. Purpose. The purpose of this test is to monitor the device parameter for a discontinuity under the specified Apparatus. The apparatus used in this test shall be capable of varying the temperature from the specified high temperature to-65 C and return to the specified high temperature while the parameter is being Procedure. The voltage and current specified in the detail specification shall be applied to the terminals and the parametermonitored from the specified high temperature to -65 C and return to the specified high temperature. The dew point temperature isindicated by a sharp discontinuity in the parameter being measured with respect to temperature. If no discontinuity is observed, it shall beassumed that the dew point is at a temperature lower than -65 C and the DUT is Summary. The following conditions shall be specified in the detail temperature (high) (see 2.). voltage and current (see 3.). parameter (see 3.).METHOD SEAL1. Purpose. The purpose of this test is to determine the hermeticity of semiconductor devices with designed internal leak rate. Standard leak rate is defined as that quantity of dry air at +25qC in atmospheric cubic centimeters flowingthrough a leak or multiple leak paths per second when the high-pressure side is at 15 psi (101 kPa) and the low-pressure sideis at a pressure of not greater than .0193 psi (133 pA). Standard leak rate shall be expressed in units of atmospheric cubiccentimeters per second (atm cm3/s air). leak rate. Measured leak rate (R1) is defined as the leak rate of a given package as measured under specifiedconditions and employing a specified test medium. Measured leak rate shall be expressed in units of atmospheric cubiccentimeters per second (atm cm3/s of the gas medium used for the test). For purposes of comparison with rates determinedby other methods of testing, the measured leak rates must be converted to the equivalent standard leak rates, (converted to airequivalents). standard leak rate. The equivalent standard leak rate (L) of a given package, with a measured leak rate (R1), isdefined as the leak rate of the same package with the same leak geometry, that would exist under the standard leak rate. Theequivalent standard leak rate shall be expressed in units of atmospheric cubic centimeters per second (atm cm3/s) (air).NOTE: The leak rate measurements are not necessarily performed with a one atmosphere differential, as implied by the standard leak rate. The equivalent conversion represents gas medium Test leaks. Test conditions A, B, C, D, E, J, K, or L should be specified for gross leaks.(1)Test condition A: Radioisotope wet gross leak test (see 4.).(2)Test condition B: Radioisotope dry gross leak test (see 5.).(3)Test condition C: Fluorocarbon gross leak (see 6.).(4)Test condition D: Bubble test (see 3b(1)).(5)Test condition E: Penetrant dye gross leak (see 8.).(6)Test condition J: Weight gain gross leak (see 11.).(7)Test condition K: Fluorocarbon vapor detection gross leak (see 12.).(8)Test condition L1: Optical gross leak (see 13). leaks. Test condition D may be specified when a sensitivity of 1 x 10-3 atm cm3/s or greater will satisfy condition shall not be used for devices that have internal free volumes of less than 1 leak. Test condition G, H, or L should be specified for the fine leak test.(1)Test condition G: Radioisotope fine leak test (see 9.).(2)Test conditions H1 and H2: Tracer gas leak test (Helium) (see 10.).(3)Test conditions L2: Optical fine leak test (see 13.).METHOD of and gross leak test procedure. Unless otherwise specified by applicable detail specification, tests shall be conducted inaccordance with table 1071-I. When specified (see 14.) measurements after test shall be conducted following the leak testprocedures. Where bomb pressure specified exceeds the device package capability, alternate pressure, exposure time, anddwell time conditions may be used provided they satisfy the leak rate, pressure, and time relationships which apply andprovided no less than 30 psi (207 kPa) bomb pressure is applied in any case, or for condition L1, a minimum 10 psi differentialtest pressure is and gross leak tests shall be conducted in accordance with the requirements and procedures of the specified testcondition. Testing order shall utilize only the all-dry gas tests first, followed by any liquid immersion gross leak test ( ; theoption to use the radioisotope gross and fine leak test conditions B and G1, may be used together, or in succession, as longas the minimum test requirements are met). Optical gross leak test (L1) is an all-dry gas test and can be used before any fineleak test. If any other gross leak test is used, (condition A, C, D, E, F, J, or K), the sequence of testing must use the dry gasfine leak test first, followed by the gross leak test except in accordance with 15a. When batch testing (more than one devicein the leak detector at one time) is used in performing test condition G, H1, H2, and a reject condition occurs it shall be notedas a batch failure. Each device may then be tested individually one time for acceptance if all devices in the batch are retestedwithin one hour after removal from the tracer gas pressurization chamber. For condition G, only, devices may be batchretested for acceptance providing all retesting is completed within one hour after removal from the tracer gas pressurizationchamber. For condition K only, devices that are batch tested, and indicate a reject condition, may be retested individually onetime using the procedure of herein, except that repressurization is not required if the devices are immersed in detectorfluid within 20 seconds after completion of the first test, and they remain in the bath until 1071-I. Required test sequence. ||||| Volume (cm3) | Fine leak condition | Gross leak condition |||||| | G, H1, H2, L2| A, C, D, E, J 1/, K 2/, L1|||||| > | G, H1, H2, L2| A, B, C, D, E, K, L1|||||| > | J 3/| J 3/|| | | |1/ Condition J cannot be used for packages whose internal volume is < Condition D cannot be used for packages whose internal volume is d 1 Condition J may be used as a single test for devices with an internal cavity volume of > cm3 provided the specified requirements can be satisfied by a leak rate of 1 x 10-6 atm cm3 Test condition A, radioisotope wet gross leak Apparatus. The apparatus required for the seal test shall be as tracer gas activation equipment consisting of a scintillation crystal, photomultiplier tube, preamplifier, ratemeter, and krypton-85 referencestandards. The counting station shall be of sufficient sensitivity to determine through the device wall the radiation level of anykrypton-85 tracer gas present within the device. The counting station shall have a minimum sensitivity corresponding to a leakrate of 10-9 atm cc/s of krypton-85 and shall be calibrated at least once every working shift using krypton-85 referencestandards and following the equipment manufacturer's container of sufficient volume to allow the devices to be covered with oil and to be degreased with a :(1)Hydrocarbon vacuum pump oil. The solution shall be kept clean and free of contaminants.(2)Solvent capable of degreasing the tracer gas consisting of a mixture of krypton-85 and dry nitrogen. The concentration of krypton-85 in dry nitrogen shall beno less than 100 microcuries per atmospheric cubic centimeter. This value shall be determined at least once each 30 days,following manufacturer's procedure, and recorded in accordance with the calibration requirements of this Procedure. The devices shall be immersed in the oil and evacuated to a pressure of 10 torr or less, for 10 minutes, and thenpressurized for one hour at 310 kPa (45 psi) minimum. The devices shall be removed from the oil and flushed with solvent to remove allof the surface oil. The devices shall then be placed in the radioisotope pressurization tank, and the tank evacuated to a pressure of x10-3 psi (67 Pa). The devices shall then be pressurized to a minimum of three atmospheres absolute pressure of krypton-85/nitrogengas mixture for two to five minutes. The gas mixture shall then be evacuated to storage until a pressure of to psi (267 to333 Pa) maximum exists in the tank. This evacuation shall be completed in two minutes maximum. The tank shall then be filled with air,and the devices immediately removed from the tank and leak tested within 15 minutes after gas exposure, with a scintillation crystalequipped counting station. Any device indicating 1,000 c/m or greater above the ambient background of the counting station shall beconsidered a gross Personnel precautions. Government regulations require a license for the possession and use of krypton-85 leak test regulations should be followed carefully. The personnel should be properly instructed and monitored in accordance with thelicensing Test condition B, radioisotope dry gross leak. This test shall be only to test devices that internally contain some krypton-85absorbing medium, such as electrical insulation, organic, or molecular sieve material. This test shall be permitted only if the followingrequirements are 5 to 10 mil diameter hole shall be made in a representative unit of the devices to be device shall be subjected to this test condition with a count rate from 200 to 250 counts per minute above ambientbackground. The count rate shall be made two hours after removal from the activation tank. If the device fails, this testcondition may be used, but only for those devices represented by the test unit. If the device does not fail, this test conditionshall not be Apparatus. Apparatus for this test shall consist of the tracer gas activation console containing krypton-85/dry nitrogen gas station with a minimum sensitivity of 12,000 counts per minute per microcurie of krypton-85 tracer gas and aminimum detectable count rate of 100 counts per minute above background gas mixture of krypton-85/dry nitrogen with a minimum allowable specific activity of 100 microcuries per atmosphericcubic centimeter. The specific activity of the krypton-85/dry nitrogen mixture shall be determined on a once-a-month basis asa Procedure. The devices shall be placed in a radioactive tracer gas activation tank and the tank shall be evacuated to a pressurenot to exceed x 10-3 psi (67 Pa). The devices shall then be subjected to a minimum of 25 psi (173 kPag) of krypton-85/dry nitrogengas mixture for 2 to 5 minutes. The gas mixture shall then be evacuated to storage until a pressure of psi (670 Pa) maximumexists in the activation tank. This evacuation shall be complete in three minutes maximum. The activation tank shall then be backfilledwith air (air wash). The devices shall then be removed from the activation tank and leak tested within 30 minutes after gas exposure witha scintillation-crystal-equipped counting station. Any device indicating 200 counts per minute or greater above the ambient background ofthe counting station shall be considered a gross leak Personnel precautions. See Test condition C, liquid (fluorocarbon) gross Apparatus. Apparatus for this test shall consist of the vacuum/pressure chamber for the evacuation and subsequent pressure bombing of devices up to 90 psi (618 kPa) for amaximum of 24 suitable observation container with provisions to maintain the indicator fluid at a temperature of +125qC 5qC (+100qC forGermanium transistors with temperature rating of +100qC maximum) and a filtration system capable of removing particlesgreater than one micrometer in size from the magnifier capable of magnifying an object to 30 times its normal size (4 to 120 diopters) for observation of bubblesemanating from devices when immersed in the indicator of type I detector fluids and type II indicator fluids as specified in table 1071-II. Physical property requirements of perfluorocarbon fluids. 1/ ||||||| Property| Type I| Type II| Type III| ASTM|| | | | | test method |||||||| Boiling point (qC) | 50-95 | 140-200 | 50-110 | D-1120 |||||||| Surface tension (dynes/|| < 20|| D-971|| cm) at +25qC | | | | D-1331 |||||||| Density at +25qC (gm/ml) | > | > | > | D-941 |||||||| Density at +125qC (gm/ml) | | ,> | | D-941 |||||||| Dielectric strength| > 300| > 300| > 300| 877|| (volts/mil) | | | | |||||||| Residue (Pgm/gm) | < 50 | < 50 | < 50 | D-2109 |||||| Appearance | Clear colorless | NA |1/ Perfluorocarbons contain no chlorine or 1071-III. Condition C and K pressurization conditions. |||| Pressure| Minimum pressurization|| psia (minimum)| time (hour) |||||| | Condition C | Condition K |||||| 30 | | 12 |||||| 45 | 8 | 4 |||||| 60 | 4 | 2 |||||| 75 | 2 | 1 |||||| 90 | 1 | |||||| 105 | | N/A |METHOD lighting source capable of producing a collimated beam of at least 161,000 luxes (15,000 foot candles) in air at a distanceequal to that which the most distant device in the bath will be from the source. The lighting source shall not requirecalibration, but shall be placed for best detection of bubbles, without excessive incident or reflective glare being directedtoward calibrated instruments to indicate that test temperatures, pressures, and times are as fixtures to hold the device(s) in the indicator Procedure. The devices shall be placed in a vacuum/pressure chamber and the pressure reduced to psi (670 Pa) or lessand maintained for 30 minutes minimum, except for devices with an internal volume t cm3 this vacuum cycle may be omitted. Asufficient amount of type I detector fluid shall be admitted to cover the devices. When the vacuum cycle is performed, the fluid will beadmitted after the minimum 30 minute period but before breaking the vacuum. The devices shall then be pressurized in accordance withtable 1071-III. When the pressurization period is complete the pressure shall be released and the devices removed from the chamberwithout being removed from a bath of detector fluid for greater than 20 seconds. A holding bath may be another vessel or storage the devices are removed from the bath they shall be dried for 2 1 minutes in air prior to immersion in type II indicator fluid, whichshall be maintained at +125qC 5qC. The devices shall be immersed with the uppermost portion at a minimum depth of 2 inches ( ) below the surface of the indicator fluid, one at a time or in such a configuration that a single bubble from a single device out of agroup under observation may be clearly observed as to its occurrence and source. Unless rejected earlier, the device shall be observedagainst a dull, nonreflective black background through the magnifier, while illuminated by the lighting source, from the instant ofimmersion until expiration of a 30-second minimum observation Failure criteria. A definite stream of bubbles, or two or more bubbles originating from the same point shall be cause for Precautions. The following precautions shall be observed in conducting the fluorocarbon gross leak fluids shall be filtered through a filter system capable of removing particles greater than one micrometer priorto use. Bulk filtering and storage is permissible. Liquid which has accumulated observable quantities of particulate matterduring use shall be discarded or reclaimed by filtration for re-use. Precaution should be taken to prevent container shall be filled to assure coverage of the device to a minimum of 2 inches ( mm). to be tested shall be free of foreign materials on the surface, including conformal coatings and any markings whichmay contribute to erroneous test should be taken to prevent operator injury due to package rupture or violent evolution of bomb fluid when testinglarge Test condition D, bubble test (type II indicator fluid as specified in table 1071-II.) (NOTE: These fluids replace ethylene glycol as amedium for the gross leak bubble test.) Apparatus. Apparatus for this test shall consist of the device internal free volume of greater than 1 of sufficient volume to allow the devices to be covered with solution to a minimum depth of 2 inches ( mm).The container shall have flat sides to minimize reflections and distortions (example of an acceptable container is a battery jar). of sufficient volume maintained at no less than +125qC 5qC for the duration of the light source capable of producing a collimated beam of at least 161,000 luxes (15,000 foot candles) in air at a distanceequal to that which the most distant device in the bath will be from the source. The lighting source shall not Procedure. The devices shall be placed in the container of liquid at +125qC, immersed to a minimum depth of 2 inches ( ) for a minimum of one minute, and observed during the entire immersion period for bubbles or bubbling. Side lighting (see )shall be used to facilitate viewing the bubbles, and the devices shall be observed against a black nonreflective Failure criteria. Any device that shows one or more nonreflective attached growing bubbles, one continuous stream, or asuccession of two or more from the same point shall be considered a Test condition E, penetrant dye gross Apparatus. Apparatus for this test shall consist of the light source with peak radiation at approximately the frequency causing maximum reflection of the dye (3650 forZyglo; 4935 for Flurosecein; 5560 for Rhodamine B). chamber capable of maintaining 104 psi (719 kPa). of fluorescent dye, (such as Rhodamine B, Fluorescein, Dye-check, Zyglo, FL-50 or equivalent), mixed in accordancewith the manufacturer's magnifier capable of magnifying an object to 30 times its nominal size (4 to 120 diopters). Procedure. This test shall be permitted only on transparent glass encased devices or for destructive verification of opaquedevices. The pressure chamber shall be filled with the dye solution to a depth sufficient to completely cover all the devices. The devicesshall be placed in the solution and the chamber pressurized at 104 psi (719 kPa) minimum for three hour minimum. For device packageswhich will not withstand 105 psi (724 kPa), 60 psi (414 kPa) minimum for 10 hours may be used. The devices shall then be removed andcarefully washed, using a suitable solvent for the dye used, followed by an air jet dry. Transparent devices may be examined undermagnification capable of magnifying an object up to times its normal size (4 diopters) using ultraviolet light source of appropriatefrequency for evidence of the dye penetration. For the destructive examination of opaque devices, the devices shall be delidded andexamined internally under the magnifier using an ultraviolet light source of appropriate Failure criteria. Any evidence of dye in the cavity of the device shall constitute a Test condition G1. Radioisotope fine Apparatus. Apparatus for this test shall be as in Activation parameters. The activation pressure and soak time shall be determined in accordance with the following equation: R QS = (1) S K T P tThe parameters of equation (1) are defined as follows:QS=The maximum leak rate allowable, in atm cc/s Kr, for the devices to be per minute above the ambient background after activation if the device leak rate were exactly equal to QS. This isthe reject count above the background of both the counting equipment and the component, if it has been through priorradioactive leak specific activity, in microcuries per atmospheric cubic centimeter, of the krypton-85 tracer gas in the overall counting efficiency of the scintillation crystal in counts per minute per microcurie of krypton-85 in the internalvoid of the specific component being evaluated. This factor depends upon component configuration and dimensions ofthe scintillation crystal. The counting efficiency shall be determined in accordance with time, in hours, that the devices are to be activated. _P=Pe2 - Pi2, where Pe is the activation pressure in atmospheres absolute, and Pi is the original internal pressure of thedevices in atmospheres absolute. The activation pressure (Pe) may be established by specification or if a convenientsoak time (T) has been established, the activation pressure (Pe) can be adjusted to satisfy equation (1).t=Conversion of hours to seconds and is equal to 3,600 seconds per hour. NOTE:The complete version of equation (1) contains a factor (PO2 - ('P)2) in the numerator which is a correction factor for elevationabove sea level. PO is sea level pressure in atmospheres absolute and P is the difference in pressure, in atmospheresbetween the actual pressure at the test station and sea level pressure. For the purpose of this test method, this factor hasbeen Determination of counting efficiency (k). The counting efficiency (k) of equation (1) shall be determined as representative units of the device type being tested shall be tubulated and the internal void of the device shall bebackfilled through the tubulation with a known volume and known specific activity of krypton-85 tracer gas and the tubulationshall be sealed counts per minute shall be directly read in the shielded scintillation crystal of the counting station in which the devices areread. From this value, the counting efficiency, in counts per minute per microcurie, shall be Evaluation of surface sorption. All device encapsulations consisting of glass, metal, and ceramic or combinations thereof,including coatings and external sealants, shall be evaluated for surface sorption of krypton-85 before establishing the leak testparameters. Representative samples of the questionable material shall be subjected to the predetermined pressure and time conditionsestablished for the device configuration as specified by The samples shall then be counted every 10 minutes, with count rates noted,until the count rate becomes asymptotic with time. (This is the point in time at which surface sorption is no longer a problem.) This timelapse shall be noted and shall determine the "wait time" specified in Procedure. The devices shall be placed in the radioactive tracer gas activation tank. The activation chamber may be partially filledwith inert material to reduce pumpdown time. The tank shall be evacuated to x 10-3 psi (67 Pa). The devices shall be subjected to aminimum of 29 psi (203 kPa) absolute pressure of krypton-85/dry nitrogen mixture of 12 minutes. Actual pressure and soak time shall bedetermined in accordance with The R value in counts per minute shall not be less than 600 above background. The krypton-85/drynitrogen gas mixture shall be evacuated to storage until x 10-3 psi (67 Pa) to psi (270 Pa) pressure exists in the activation storage cycle shall be completed in three minutes maximum as measured from the end of the activation cycle or from the time theactivation tank pressure reaches 60 psi (414 kPa) if a higher bombing pressure is used. The activation tank shall then immediately bebackfilled with air (air wash). The devices shall then be removed from the activation tank and leak tested within one hour after gasexposure with a scintillation-crystal-equipped counting station. Device encapsulations that come under the requirements of shall beexposed to ambient air for a time not less than the "wait time" determined by In no case will the time between removal from theactivation chamber and test exceed one hour. This air exposure shall be performed after gas exposure but before determining leak ratewith the counting station. Device encapsulations that do not come under the requirements of may be tested without a "wait time".(The number of devices removed from pressurization for leak testing shall be limited such that the test of the last device can becompleted within one hour.) The actual leak rate of the component shall be calculated with the following equation: (Actual readout in net counts per minute) x QS Q = ------------------------------------------------------------- (2) RWhere Q = Actual leak rate in atm cc/s, and QS and R are defined in : CAUTION. Discharge of krypton 85 into the atmosphere must not exceed limits imposed by local and Federal Failure criteria. Unless otherwise specified, devices that exhibit a leak rate equal to or greater than the test limits of table1071-IV shall be considered as : CAUTION. Devices which do not exhibit a leak rate sufficient to fail seal test, may retain radioactive tracer gas in sufficientconcentration to cause soft errors in complex, small geometry 1071-IV. Test limits for radioisotope fine leak method. |||| Volume of package| QS|| (cc) | ||||| < | 1 x 10-8|| t , d | 5 x 10-8|| > | 5 x 10-7|| | | Personnel precautions. See Test condition H or H tracer gas (H ) fine leak. Test condition H1 is a "fixed" method with specified conditions in 1 2 eaccordance with table 1071-V that will ensure the test sensitivity necessary to detect the required measured leak rate (R1). Testcondition H2 is a "flexible" method that allows the variance of test conditions in accordance with the formula of to detect thespecified equivalent standard leak rate (L) at a predetermined leak rate (R1). Apparatus. Apparatus required for test conditions H1 and H2 shall consist of suitable pressure and vacuum chambers and amass spectrometer-type leak detector properly calibrated for a helium leak rate sensitivity sufficient to read measured helium leak rates of1 x 10-9 atm cm3/s and greater. The volume of the chamber used for leak rate measurement should be held to the minimum practical,since this chamber volume has an adverse effect on sensitivity limits. The leak detector indicator shall be calibrated using adiffusion-type calibrated standard leak at least once every working Procedure applicable to "fixed" and "flexible" methods. The completed devices(s) shall be placed in a sealed chamber which isthen pressurized with a tracer gas of 100 +0, -5 percent helium for the required time and pressure. The pressure shall then be relieved(an optional air nitrogen wash may be applied) and each specimen transferred to another chamber or chambers which are connected tothe evacuating system and a mass-spectrometer-type leak detector. When the chamber(s) is evacuated, any tracer gas which waspreviously forced into the specimen will thus be drawn out and indicated by the leak detector as a measured leak rate (R1). (The numberof devices removed from pressurization for leak testing shall be limited such that the test of the last device can be completed within 60minutes for test condition H1 or within the chosen value of dwell time t2 for test condition H2.) Evaluation of surface sorption. All device encapsulations consisting of glass, metal, and ceramic or combinations thereofincluding coatings and external sealants, shall be evaluated for surface sorption of helium before establishing the leak test specimens of the questionable devices should be opened and all parts of each device as a unit shall be subjected to thepredetermined pressure and time conditions established for the device configuration as specified in table 1071-V and Themeasured leak rate for each device shall be monitored and the lapsed time shall be determined for the indicated leak rate to fall to R1as specified in table 1071-V for test condition H1 or as predetermined for test condition H2. The average of the lapsed time following therelease of pressure will determine the minimum usable dwell time. Note that the sensitivity of measurement increases as this backgroundindicated-leak-rate decreases relative to the R1 reject level. Alternately, whole (unopened) specimens of the questionable devices shallbe subjected to the same process; then, the shorted value of lapsed time so obtained will determine the minimum dwell time. The fixedmethod will not be used if the consequent dwell time exceeds the value specified in table 1071-V. It is noted that sorption may vary withpressure and time of exposure so that some trial may be required before satisfactory exposure values are Test condition H , fixed method. The device(s) shall be tested using the appropriate conditions specified in table 11071-V for the internal cavity volumes of the package under test. The t1 is the time under pressure and time t2 is the maximum timeallowed after the release of pressure before the device shall be read. The fixed method shall not be used if the maximum standard leakrate limit given in the detail specification is less than the limits specified herein for the flexible 1071-V. Fixed conditions for test condition H1. |||||| Bomb condition | || Volume of|||| R1 reject|| package| kPa r15| Exposure time in hours|Maximum dwell| limit|| (cm3)| (psi) r2| (t1)| time (hour)| (atm cm3/s) || | | (+ - ) | | ||| || ||| < | 517 (75)| 2| 1| 5 x 10-8||> < | 517 (75)| 4| 1| 5 x 10-8||> < | 310 (45)| 2| 1| 1 x 10-7||> < | 310 (45)| 5| 1| 5 x 10-6||> < | 310 (45)| 10| 1| 5 x 10-6|| | | | | | Test condition H , flexible method. Values for bomb pressure, exposure time, and dwell time shall be chosen such 2that actual measured tracer gas leak rate (R1) readings obtained for the DUTs (if defective) will be greater than the minimumdetectable leak rate capability of a mass spectrometer. The devices shall be subjected to a minimum of 29 psi (203 kPa) of heliumatmosphere. The chosen values of pressurization and time of pressurization, in conjunction with the value of the internal volume of thedevice package to be tested and the maximum equivalent standard leak rate (L) limit as specified in , shall be used to calculatethe measured leak rate (R1) limit using the following formula:Where:R1 = The measured leak rate of tracer gas (He) through the leak in atm cm3 = The equivalent standard leak rate in atm cm3 = The pressure of exposure in atmospheres = 1 standard = The time of exposure to Pe in = The dwell time between release of pressure and leak detection in = The internal volume of the device package cavity in cubic MIL-STD-750DThe minimum detectable leak rate shall be determined as in and shall be taken as the indicated value corresponding to a lapsedtime tO < t2. The lapsed time tO shall be taken as the minimum usable dwell time, and leak testing shall be accomplished in the intervalbetween tO and t2. Alternately, pressurization parameters may be chosen from the fine leak approximate solution of equation (3) for L < 1x 10-5 aswith a graphical representation given on figure 1071-1. If chosen dwell time t2 is greater than 60 minutes, equation (2) shall be used todetermine an R1 value which will assure a maximum detectable standard leak rate large enough to overlap with the selected gross leaktest condition. Alternately, the largest detectable leak rate L as a function of dwell time may be obtained from the approximate solutionwith graphical representation given on figure 1071-2. In each case (equations (4) and (5)) R1 shall be taken large compared to theminimum detectable value. 1 Failure criteria. Unless otherwise specified, devices with an internal cavity volume of cm3 or less shall not be accepted ifthe equivalent standard leak rate (L) exceeds 5 x 10-8 atm cm3/s. Devices with an internal cavity volume greater than cm3 andequal to or less than cm3 shall not be accepted if the equivalent standard leak rate (L) exceeds 1 x 10-7 atm cm3/s. Devices with aninternal cavity volume greater than cm3 shall not be accepted if the equivalent standard leak rate (L) exceeds 1 x 10-6 atm cm3 Test condition J, weight gain gross Apparatus. Apparatus for this test shall consist of the vacuum/pressure chamber for the evacuation and subsequent pressure bombing of devices up to 90 psi (618 kPa) for up to10 analytical balance capable of weighing the devices accurately to source of type III detector fluid as specified in table filtration system capable of removing particles greater than one micrometer in size from the calibrated instruments to measure test pressures and suitable 1/From "Standard Recommended Practices for Determining Hermeticity of Electron Devices with a Helium Mass Spectrometer LeakDetector," ASTM Designation F134, Annual book of ASTM Standards, Pt. 43 November MIL-STD-750D Procedure. The devices shall be cleaned by placing them in a container of a suitable solvent at +25qC and allowed then to soakfor two minutes minimum. The devices shall then be removed and placed in an oven at +125qC 5qC for one hour minimum, after whichthey shall be allowed to cool to room ambient temperature. Each device shall be weighed and the initial weight recorded or the devicesmay be categorized into cells as follows: Devices having a volume of cm3 shall be categorized in cells of milligram incrementsand devices with volumes > cm3 shall be categorized in cells of milligram increments. The devices shall be placed in avacuum/pressure chamber and the pressure reduced to psi (667 Pa) and maintained for one hour except that for devices with aninternal cavity volume cm3, this vacuum cycle may be omitted. A sufficient amount of type III detector fluorocarbon fluid shall beadmitted to the pressure chamber to cover the devices. When the vacuum cycle is performed, the fluid shall be admitted after the onehour period but before breaking the vacuum. The devices shall then be pressurized to 75 psi (517 kPa) except that 618 kPa (90 psia)shall be used when the vacuum has been omitted. The pressure shall be maintained for two hours minimum. If the devices will notwithstand the 75 psi (517 kPa) test pressure, the pressure may be lowered to 45 psi (310 kPa) with the vacuum cycle and pressuremaintained for 10 hours minimum. Upon completion of the pressurization period, the pressure shall be released and the devices removedfrom the pressure chamber and retained in a bath of the fluorocarbon fluid. When the devices are removed from the fluid they shall be airdried for 2 1 minutes prior to weighing. The devices shall be transferred singly to the balance and the weight or weight category of eachdevice determined. All devices shall be tested within four minutes following removal from the fluid. The delta weight shall be calculatedfrom the record of the initial weight and the post weight of the device. Devices which were categorized shall be separated into twogroups, one of which shall be the devices which shifted one cell or less, and the other devices which shifted more than one Failure criteria. A device shall be rejected if it gains milligram or more and has an internal volume of cm3 and or more if the volume is > cm3. If the devices are categorized, any device which gains enough weight to cause the deviceto shift by more than one cell shall be considered a reject. A device which loses weight of an amount which if gained would cause thedevice to be rejected may be retested after it is baked at +125qC 5qC for a period of 8 hours Test condition K, fluorocarbon vapor Apparatus. Apparatus for this test shall consist vacuum/pressure chamber for the evacuation and subsequent pressure bombing of devices up to 90 psi (620 kPa) for up to12 fluorocarbon vapor detection system capable of detecting vapor quantities equivalent to milligram of type I source of type I detector fluid specified in table calibrated instruments to indicate that test, purge times, and temperatures are as specified. The detection systemshall be calibrated at least once each shift when production occurs by introducing 1 microliter of type I detector fluid into thetest chamber. The resulting reading shall be adjusted in accordance with the manufacturer's vapor detector used for condition K shall be calibrated at least once each working shift using a type I fluid calibrationsource, and following the manufacturer's Procedure. The devices shall be placed in a vacuum/pressure chamber and the pressure reduced to 5 torr or less andmaintained for 30 minutes minimum. A sufficient amount of type I detector fluid shall be admitted to the pressure chamber to cover thedevices. The fluid shall be admitted after the 30 minute vacuum period but before breaking the vacuum. The devices shall then bepressurized and maintained in accordance with table 1071-III. Upon completion of the pressurization period, the pressure shall bereleased, the devices removed from the pressure chamber without being removed from the detector fluid for more than 20 seconds andthen retained in a bath of fluorocarbon fluid. When the devices are removed from the fluid they shall be air dried for a minimum of 20seconds and a maximum of 5 minutes prior to the test cycle. If the type I detector fluid has a boiling point of less than +80qC, themaximum drying time shall be 3 minutes. The devices shall then be tested with a fluorocarbon vapor detection system that is calibrated inaccordance with "Purge" time shall be in accordance with table 1071-VI. Test time shall be a minimum of seconds unless thedevice is rejected earlier. The system's purge and test chambers shall be at a temperature of +125qC 5qC. Test time shall be minimum with the purge and test chambers at a temperature of +150qC :Test temperature shall be measured at the chamber surface that is in contact with the Failure criteria. A device shall be rejected if the detector instrumentation indicates more than the equivalent of milligrams oftype I detector fluid in accordance with table 1071-VI. Purge time. || || Package with internal|Purge time at +125qC 5qC|| free volume||| (cm3)| (Seconds)|| | ||| || | d5|| | ||| || | d9|| | ||| || | d13|| | |NOTE: Purge time shall be defined as the total time the device is heated prior to entering the test mode. Maximum purge time can be determined by cycling a device with a .02 to .05-inch ( to mm) hole and measuring the maximum purge time that can be used without permitting the device to escape Test condition L or L - optical gross or gross/fine leak. 1 optical inspection station capable of evacuation and/or pressurization, and subsequent detection of package calibration instrumentation to indicate test results, times and pressures are as Lid stiffness. Test condition L1 and L2 are valid only for packages with thin lids (thickness < typically for metallic lids). Thetest sensitivity is related to the extent of deformation of the lid due to the specific pressure change and the test time used. For a specificlid material ad size the following formula must be met: for condition L1: R4 / E T3 > x 10-4 (1) for condition L2: R4 / E T3 > x 10-3 (2)Where: R = The minimum width of free lid (inside braze or cavity dimension in inches). E = The modulus of elasticity of the lid material. Aluminum: E = 10 x 106 lb/in2 Kovar: E = 20 x 106 lb/in2 Ceramic: E = 60 x 106 lb/in2 T = The thickness of the lid (inches).METHOD Leak sensitivity. The optical leak test shall be performed with a test pressure (Po) and time (t), which will provide the leak ratesensitivity required. The leak rate sensitivity is provided by the following equation: L = (-Vo / k2 t) In(1 - dYt / Po Lo).Where: L = The leak rate sensitivity of the test (atm-cc/sec). Vo = The volume of the package cavity (in3). k2 = The leak test gas constant (air = , He = ). t = The test duration time (seconds). dYt = The measured deformation of the package lid (inches). Po = The chamber pressure during the test (psig). Lo = The lid stiffness constant calculated from the package dimensions (inch/psi). Test condition L - optical gross leak. The completed device(s) shall be placed in the sealed test chamber. The 1optical interferometer shall be set to observe the package lid. The chamber shall then be evacuated while the deformation of the lid isbeing observed with the optical interferometer. The deformation of the lid with pressure change, and the lack of continued deformation ofthe lid with reduced pressure held for time t1 (or equivalent procedure), will be observed for each package in the field of Failure criteria. A device shall be rejected if the optical interferometer did not detect deformation of the lied as the chamberpressure was initially changed, or if the interferometer detects the lid deforming as the chamber pressure is held constant (or equivalentprocedure). Test condition L - optical gross/fine leak. The completed device(s) shall be placed in the sealed test chamber. The 2optical interferometer shall be set to observe the package lid. The chamber shall then be evacuated while the deformation of the lid isbeing observed with the optical interferometer. The deformation of the lid with pressure change, and the lack of continued deformation ofthe lid with reduced pressure held for time t1 (or equivalent procedure), will be observed for each package in the field of viewsimultaneously. The sealed test chamber is then pressurized with Helium gas to no more than 2 atmospheres. The lack of deformationof the lid is then observed with an optical interferometer to time t2 (or equivalent procedure). Failure criteria. A device shall be rejected for any of the three following criteria. If the interferometer did not detect deformationof the lid as the chamber pressure was initially changed. Or, if the interferometer detects the lid deforming form the package leaking itsentrapped internal pressure during time t1 as the pressure is held constant (or equivalent procedure). Or, if the interferometer detects thelid deforming from the package leaking in the pressurized Helium gas during time t2 as the pressure is held constant (or equivalentprocedure).14. Summary. The following conditions shall be specified in the applicable detail condition letter when a specific test is to be applied (see 3.). or reject leak rate for test conditions G, H1, or H2 when other than the accept or reject leak rate specified hereinapplies (see , , and ). applicable, measurements after test (see 3.). acceptability for test conditions G and H (see 9.). For K, see of performance of fine and gross if other than fine followed by gross (see 3.).METHOD 15. fine leak test shall be performed first if condition A, B, or E is used for gross leak. Gross leak may be performed prior tofine leak if condition C, D, J, K, or L is used for gross leak and provided that the vapor pressure of the fluorocarbon materialused in condition C, J, and K (which may be inside the device) is greater than 59 psi (406 kPa), TA = +125qC. The devicesshall be subjected to a bake at this temperature for a minimum of one hour prior to performing the fine leak test. Thissequence should be true regardless of whether the leak tests are part of a screening sequence or are included as group B orgroup C test conditions A through E, K, and L1, the maximum allowable leak rate should not be specified because these tests are"go"/"no-go" type tests that do not provide an indication of actual leak rate. (Although test conditions A, B, K, and L1 have adefinite quantitative measurement to be met, they are still considered "go"/"no-go" tests.) retesting devices to test conditions G and H, the history of device exposure to helium and krypton-85, including dates,backfilling performed, tracer gas concentrations, pressure, and time exposed, should be known in order to ensure value of equivalent standard leak rate as a function of pressurization conditions and indicated leak rate as computedfrom the approximate solution, for small leaks where dwell time t2 is not a significant factor. The reject level R2 shall be takenlarger relative to the minimum detectable R 1071-1. Smallest detectable test limit of equivalent standard leak rate as a function of dwell time, pressurization, and indicated leak rateas computed from the approximate solution, ( , for larger leaks where internal pressurization is complete).FIGURE 1071-2. Largest detectable SeriesMechanical characteristics testsMIL-STD-750DMETHOD LEAD TENSILE TEST1. Purpose. The purpose of this test method is to establish the capability of axial lead glass body diodes to be free of intermittents oropens when measured in the forward mode under conditions of tensile stress and controlled temperature. This test may be Equipment or volt meter and constant current source capable of supplying 100 mA of dc current to the DUT. A batterysupply is preferred but if a constant current supply is used, a voltage clamp of approximately five volts shall cell with 10 pounds full scale dial (or equivalent) capable of measuring 8 pounds 10 test fixture capable of clamping both ends of the diode while applying an 8-pound axial pull. One clamp must beelectrically isolated allowing the diode forward voltage to be air supply capable of heating the diode ambient to TA = +150 C 5 C. (TJ approximately +175 C.)3. Procedure. The diode under test shall be mounted in the pull test fixture. The electrical monitoring equipment shall be connected tothe diode leads. A forward current of 100 mA is passed through the diode while noting the forward voltage. The ambient temperature ofthe diode is then increased to 150 C. NOTE: The diode junction temperature (TJ) will be approximately +25 C higher than ambient (TJapproximately +175 C) due to the thermal resistance of the diode when testing small (computer) diodes at 100 mA dc in the forwarddirection. A silicon diode (computer type) also has an approximate negative mV/ C temperature coefficient at 100 mA. Therefore a150 mV decline (100 mV minimum) in voltage should be expected during the ambient temperature increase (from +25 C to +150 C).After stabilizing at this temperature, then the axial lead pull force of eight pounds shall be applied while observing the forward Criteria for rejection. An acceptable device shall not exhibit a forward voltage increase of more than 30 mV during the 8-pound instability or open is cause for Summary. The following conditions shall be specified in the detailed test temperature, if other than +150 C 5 current, if other than 100 mA tensile stress, if other than change in forward voltage, if other than 30 2006CONSTANT ACCELERATION1. Purpose. The constant acceleration test is used to determine the effect on devices of a centrifugal force. This test is anaccelerated test designed to indicate types of structural and mechanical weaknesses not necessarily detected in shock and Apparatus. Constant acceleration tests shall be made on an apparatus capable of meeting the minimum requirements of theindividual Procedure. The device shall be restrained by its case, or by normal mountings, and the leads or cables secured. A centrifugalacceleration of the value specified shall then be applied to the device for one minute in each of the orientations X1, X2, Y1, Y2, Z1, and Z2. The acceleration shall be increased gradually, to the value specified, in not less than 20 seconds. The acceleration shall bedecreased gradually to zero in not less than 20 Summary. The following conditions shall be specified in the detail of centrifugal force to be applied, in gravity units (g) (see 3.). to be made after 20061/2MIL-STD-750DMETHOD Purpose. This test is intended to determine the ability of the devices to withstand moderately severe shocks such as would beproduced by rough handling, transportation or field operation. Shocks of this type may disturb operating characteristics or cause damagesimilar to that resulting from excessive vibration, particularly if the shock pulses are Apparatus. The shock testing apparatus shall be capable of providing shock pulses of the specified peak acceleration and pulseduration to the body of the device. The acceleration pulse, as determined from the output of a transducer with a natural frequency greaterthan or equal to five times the frequency of the shock pulse being established, shall be a half-sine waveform with an allowable distortionnot greater than 20 percent of the specified peak acceleration. The pulse duration shall be measured between the points at 10 percentof the peak acceleration during rise time and at 10 percent of the peak acceleration during decay time. Absolute tolerances of the pulseduration shall be the greater of milliseconds (ms) or 15 percent of the specified duration for specified durations of 2 ms andgreater. For specified duration less than 2 ms, absolute tolerances shall be the greater of ms or 30 percent of the Procedure. The shock-testing apparatus shall be mounted on a sturdy laboratory table or equivalent base and leveled before device shall be rigidly mounted or restrained by its case with suitable protection for the leads. The device shall be subjected to thespecified number of blows in the specified direction. For each blow, the carriage shall be raised to the height necessary for obtaining thespecified acceleration and then allowed to fall. Means may be provided to prevent the carriage from striking the anvil a second load conditions and measurements to be taken during the shock test, if applicable, shall be as specified. End pointmeasurements shall be as Summary. The following conditions shall be as specified in the detail and duration of pulse (see 2.). and direction of blows (see 3.). conditions, if applicable (see 3.). during shock, if applicable (see 3.). point measurements (see 3.).METHOD ATTACH INTEGRITY1. Purpose. The purpose of this test is to establish the integrity of the semiconductor die attachment to the package header or Apparatus. The test equipment shall consist of a force-applying instrument with an accuracy of 5 percent of full scale or 50grams, whichever is less. A circular dynamometer with a lever arm or a linear motion force-applying instrument may be used to apply theforce required for testing. The test equipment shall have the following die contact tool which applies a uniform distribution of the force gradually to an edge of the die (see figure 2017-1). to assure that the face of the die contact tool is perpendicular to the die mounting plane of the header or rotational capability, relative to the header/substrate holding fixture and the die contact tool, to facilitate line contact parallel tothe edge of the die; the tool applying the force to the die shall contact the die edge from end-to-end (see figure 2017-2). binocular microscope with a minimum magnification of 10X and sufficient lighting for visual inspection of the die and diecontact tool interface during apparatus for devices with a die area less than X 10-4 in2 instead of a calibrated instrument. Any hand held toolmay be used. The general requirements of , , and above shall apply. The tool which shall apply a uniformperpendicular force to the edge of the die (see figures 2017-1, 2017-2, and 2017-3) and a microscope with a minimummagnification of 10X shall be for test condition C: A hammer, chisel, or spring loaded punch are Test condition A die shear. For die directly bonded to a header or Procedure. The test shall be conducted as defined herein or to the test conditions specified in the applicable detail specificationconsistent with the particular part construction. All die strength tests shall be counted and the specific sampling, acceptance, and addedsample provisions shall be observed, as applicable. (This test shall be considered destructive.) Shear strength. A force sufficient to shear the die from its mounting or equal to twice the minimum specified shear strength (seefigure 2017-4), whichever occurs first, shall be applied to the die using the apparatus of 2 a linear motion force-applying instrument is used, the direction of the applied force shall be parallel with the plane of theheader or substrate and perpendicular to the edge of the die being a circular dynamometer with a lever arm is employed to apply the force required for testing, it shall be pivoted about thelever arm axis and the motion shall be parallel with the plane of the header or substrate and perpendicular to the edge of thedie being tested. The contact tool attached to the lever arm shall be at a proper distance to assure an accurate value ofapplied die contact tool shall apply a force gradually from zero to a specified value against an edge of the die which most closelyapproximates a 90 angle with the base of the header or substrate to which it is bonded (see figure 2017-3). For rectangulardie, the force shall be applied perpendicular to the longer side of the die. When constrained by package configurations, anyavailable side of the die may be tested if the above options are not of initial contact with the die edge and during the application of force the relative position of the contact tool shall not movevertically such that contact is made with the header/substrate or die attach material. If the tool rides over the die, a new diemay be substituted or the die may be repositioned, provided that the requirements of are Criteria for device Failure criteria. A device will be considered a failure if the die bond shears as a force less than the minimum shear strength requirements specified on figure 2017-4 ( X line). a force less than times ( X line) the minimum shear strength requirements ( X line) specified on figure2017-4 and evidence of adhesion, of the die attach material, less than 50 percent of the die attach a force less than times ( X line) the minimum shear strength requirements ( X line) specified on figure 2017-4and evidence of adhesion, of the die attach material, less than 25 percent of the die attach a force less than times ( X line) the minimum shear strength requirements ( X line) specified on figure 2017-4and evidence of less than 10 percent adhesion of the die attach Acceptance criteria. A device will be considered acceptable if the die not shear with a force equal to or greater than times ( X line) the minimum shear strength requirements ( Xline) specified on figure with evidence of remaining semiconductor material equal to or greater than 50 percent of the die attach arearegardless of the shearing force applied. (This criteria applicable only for devices with die area less than X 10-4 in2( mm2)).NOTE:Residual semiconductor material attached in discrete areas of the die attach medium shall be considered as evidence of Separation categories. When specified, the force required to achieve separation and the category of the separation shall bedefined of the die with residual silicon of die from die attach of die and die attach material from Summary. The following details shall be specified in the individual minimum die attach strength if other that shown on figure condition size and accept 2017-1. Uniform force 2017-2. Rotational 2017-3. Perpendicular force 2017-4. Die shear strength criteria (minimum force versus die attach area).METHOD Test condition B, mechanical impact. Test condition B may be used on devices which have a metallurgical bond between a headeror contact plate and the silicon die on only one side of the die and is to be used for those devices with a contact plate bonded to bothsides of the die or to one side of the die with the other side bonded to a header. This method shall not be used for die with area less square Procedure. The die assemblies are placed on a suitable anvil. For die with a contact plate or header on only one side, the die isstruck with a ball peen hammer such that the silicon is shattered. The silicon will not be adhered to those areas of the bond where solder,braze, or alloy voids exist and the voids will thus be visible. The contact plate or header can now be visually examined to determine thesize and density of any voids. The size and density of the voids are compared to the established visual standards for acceptable dieattachment. For die with both sides die attached (a contact plate on both sides or a header on one side and contact plate on the other)the die can be struck with a hammer on one contact plate or cleaved by striking with a chisel on the edge. If cleaved with a chisel, eachside should be struck with a hammer to break free any voided silicon. Visual comparison to the standards is then done as Precautions. The following precautions shall be observed during of a chisel or hammer can result in flying debris. Eye protection and protective clothing must be of the silicon can result in the exposure of sharp edges. Care in handling must be taken to avoid Failure criteria. A device will be considered a single void that has an area greater than 3 percent of the total die sum total of all void areas exceeds 6 percent of the total die Summary. The following details shall be specified in the individual test condition size per batch or Purpose. The purpose of this test method is to determine the solderability of all terminations which are normally joined by asoldering operation. This determination is made on the basis of the ability of these terminations to be wetted by a coating of solder, and topredict a suitable fillet when soldered. These procedures will verify that the treatment used in the manufacturing process to facilitatesoldering is satisfactory and that solder has been applied to the required portion of the part which is designed to accommodate a solderconnection. An accelerated aging test is included in this test method which simulates natural aging under a combination of variousstorage conditions that have different deleterious Terms and definitions. The definition of terms shall be in accordance with the Solderability. The property of a metal to be wetted by Wetting. The formulation of a relatively uniform, smooth, and unbroken film of solder, adherent to a base Porosity. A condition of a solder coating with a spongy appearing, uneven surface which contains a concentration of smallpinholes and pits. See figure Non-wetting. A condition whereby a surface has contacted molten solder, but the solder has not adhered to all of the surface,and the surface tested remains exposed. See figure Pinholes and voids. Small holes occurring as imperfections which penetrate entirely through the solder layer. See figures2026-1, 2026-2, and Dewetting. A condition which results when molten solder has coated a surface and then receded leaving irregularly shapedmounds of solder separated by areas covered with a thin solder film, and where the base metal is not exposed. See figure Foreign material. Particles of material located on, but different from the lead material or coating. See figure Solder and flux minimum application Dual-in-line packages. The location at which the termination widens to its maximum shoulder dimension, or to the packagebase plane, whichever is the furthest point from the Radial lead packages ( , flat package, top brazed quads). A location on the lead, no greater than inch from Axial lead packages ( , TO cans, PGA). A location on the lead that is no greater than inch from the body of thepackage, the seating plane, or the standoff, whichever is the furthest from the glass Leaded chip carrier ( , J bend, gull wing). A location on the leads equal to an extension of the base plane onto the leads, orthe point at which the lead Leadless chip carriers. The location which is 50 percent of the distance between the top of the castellation and the Thread mounted devices with crimped (flattered) hole punched terminals. The flat portion or .050 inches below the bottom ofthe terminal hole toward the device body, which is of 9MIL-STD-750D2. Solder pot. A static solder pot of sufficient size to contain at least 2 pounds of solder shall be used. The apparatus shall becapable of maintaining the solder at the temperature specified in (NOTE: A wave or flow pot may be used provided it is modified toprovide a totally "static" condition at the time of immersion). Dipping mechanism. A dipping mechanism capable of controlling the rates of immersion and emersion of the terminations andproviding a dwell time (total time at the required depth) in the solder bath as specified in shall be used. The sample holder shall notcome in contact with the solder Optical equipment. A binocular optical system capable of providing a minimum magnification of 10X, +10X -0X shall be Lighting equipment. A lighting system shall be used that will provide a uniform nonglare, nondirectional illumination of Steam aging equipment. A noncorrodable container and cover of sufficient size to allow the placement of specimens inside thevessel shall be used. The specimens shall be placed such that the lowest portion of the specimen shall be inch ( mm) minimumto 2 inch ( mm) maximum above the surface of the boiling water (see ). A suitable method of supporting the specimens shall beimprovised using noncontaminating material. The apparatus shall be capable of having the specified temperature verified as required Cleaning of the system. The apparatus shall be drained and cleaned at least once per month or prior to use. More frequentcleaning may be necessary. No contaminating solvents shall be Solder iron. A conduction temperature controlled solder iron of appropriate thermal capacity adequate to allow solder connection tobe made solidly and maintain proper solder temperature throughout the solder Flux. The flux shall conform to type "R" of MIL-F-14256 (25 percent nominal solids, as provided for by IPC, by weight), flux,soldering, liquid (rosin base). The customer or user may, at their option, use "RMA" flux. Flux with 25 percent nominal solids Solder. The solder shall conform to type "S", composition Sn60 or Sn63, of QQ-S-571, solder, tin alloy, tin-lead alloy, and Water. The water to be used for steam aging shall be either distilled or : These materials may involve substances that are flammable, toxic to eyes, skin, respiratory tract, or present a serious burn potential. Eye and skin protection should be used. Heat resistance gloves should be used when handling hot Standard copper wrapping wire. The standard wrapping wire specified in shall be fabricated from type S , soft or drawn andannealed, uncoated in accordance with QQ-W-343, Wire, Electrical and Nonelectrical, Copper (Uninsulated). The diameter of thewrapping wire shall be .025 .005 inch. The preparation of the wrapping wire shall be as follows:a. Straighten and cut wire into convenient lengths (2 inches ( mm) minimum).b. Degrease and clean as necessary to ensure wire surface is free of Immersion in flux (MIL-F-14256, type RMA).d. Dip in molten solder for 5 seconds at 245 C 5 C (473 F 9 F).e. To remove or dissolve the residual type RMA flux, wash or rinse in isopropyl Standard wrapping wire shall be stored in a clean, covered container if not used : All chemicals shall be of commercial grade or better. Fresh solvents shall be used as often as is necessary to preclude : The above steps may involve substances that are flammable, toxic to eyes, skin , and respiratory tract, or present a serious burn potential. Eye and skin protection are required, including heat resistant gloves when handling hot Procedure. The test procedure shall be performed on the number of terminations specified in the individual specification. The testmay be performed just prior to packaging for storage or shipment, immediately upon removal from the manufacturers' protectivepackaging or as a qualification or QCI test. The sample shall be selected at random. During handling, special care shall be exercised toprevent the surfaces being tested from being abraded or contaminated by grease, perspiration, or abnormal atmospheres. The testprocedure shall consist of the following preparation of the specimens (see ), if of all specimens (see ). of flux and solder (see and ). and evaluation of the tested portions of the terminations upon completion of the solder process (see ). Preparation of Sample preparation. No wiping, cleaning, scraping, or abrasive cleaning of the terminations shall be performed prior to special preparation of the terminations, such as bending or reorientation prior to the test, shall be specified in the Steam aging. Prior to the application of the flux and subsequent solder dips, all specimens assigned to this test shall be subjectedto aging by exposure of the surfaces to be tested to water vapor in the apparatus specified in The water vapor temperature at thecomponent lead level shall be in accordance with table 2026-I for an uninterrupted 8 hours. Aging may be interrupted once for 10minutes maximum. The devices shall be removed from the test apparatus upon completion of the specified test 2026-I. Altitude versus steam temperature. |||| Altitude (feet)| Steam temperature|| | (0 +3 -5 C) ||||| 0 - 2,000| 91|| 2,001 - 4,000| 89|| 4,001 - 6,000| 87|| Greater than 6,000 | 85 | Drying and storage procedures. Upon removing the test specimens from the apparatus, the parts may be dried using one of thefollowing dry on a noncontaminating at 100 C maximum for no more than 1 hour in a dry atmosphere (dry nitrogen atmosphere is recommended.) dry at ambient :Parts not solderability tested within 2 hours after removal from the aging apparatus shall be stored in a desiccant jar or drynitrogen cabinet up to 72 hours before testing. The parts shall not be used for testing if they exceed the Solder dip Application of the flux. The terminations to be tested shall be immersed in flux maintained at room ambient temperature. Unlessotherwise specified in the individual specification, the terminations shall be immersed according to The terminations to be testedshall be immersed in the flux for 5 to 10 seconds, and shall be allowed to drain for 5 to 20 seconds prior to dipping in the solder pot. Theflux shall be covered when not in use and discarded after 8 hours or maintained to specific gravity between and at +25qC anddiscarded after one week of Solder dip procedure. The dross and burned flux shall be skimmed from the surface of the molten solder prior to testing. Themolten solder shall be at a uniform temperature of +245qC 5qC (+473qF 9qF). (Stirring and skimming may not be required in wave orflow pots.) The part shall be attached to a dipping device (see ) and the flux covered terminations immersed once (except for thepossible duplicate immersion of corner terminations on leadless packages) in the molten solder to the depth specified in Thereshall be seconds maximum dwell time of the test specimens above the pot prior to immersion. The immersion and emersion ratesshall be .25 inch ( mm) per second. The dwell time in the solder shall be 5 .5 seconds. The dwell time for terminationsgreater than or equal to inch ( mm) in diameter shall be 7 seconds. After the dipping process, the part shall be allowed tocool in air. Residue flux shall be removed from the terminations by dipping the parts in isopropyl alcohol or other suitable solvent. Ifnecessary, a clean soft cloth, cotton swab, or similar appliance moistened with clean isopropyl alcohol or other suitable solvent, may beused to remove all remaining Solder dipping of gold plated terminations. Gold plated terminations may be immersed twice using one or two solder pots. Thefirst immersion is to scavenge the gold on the terminations. In the case of using a static pot, the solder shall be stirred in between thefirst and second immersion. It is recommended that a separate solder pot be used for gold plated Solder dipping diodes. During immersion, care shall be taken to prevent extreme thermal gradients along the device shall neither heat sink the diode body nor hold the unimmersed lead closer than inch from the Wire wrap terminations. Terminations not designed for solder dip application ( , turrets, lugs, posts, and other terminalconfigurations generally having specific wire attachment areas such as hole, notch, or slot). Application of standard wire wrap. Prior to application of flux and subsequent solder, the wire attach area of the termination shallbe wrapped 1 to turns using the standard wrapping wire specified in The wire shall be wrapped such that it will not move Application of flux. Flux shall be applied to both the wire wrapping and the attach area of the termination using any suitablemethod such as brushing. Excess flux may be drained from the termination prior to Solder iron procedure. The termination and wrapping wire shall be soldered using the solder specified in and the solderingiron specified in Heat shall be applied to the connection until the solder has been molten for 5 seconds minimum to 10 secondsmaximum. After soldering, the part shall be allowed to air cool. Residue flux shall be removed from the termination by dipping the part inisopropyl alcohol. If necessary, a clean soft cloth, cotton swab, or similar appliance moistened with clean isopropyl alcohol may be usedto remove any remaining flux. Wire wrap terminations may utilize solder application methods referenced in or Examination of terminations. The dipped portion of the terminations shall be examined using a binocular magnification of 10-20Xin accordance with Evaluation of solder dip terminations. The criteria for acceptable solderability dipped portion of the terminations is at least 95 percent covered by a continuous new solder . , voids, porosity, nonwetting, or dewetting that do not exceed 5 percent of the total area and any single defect areathat does not exceed 3 percent of the total test customer or user of the component may establish a critical portion of the termination within the dipped area. Thecustomer or user has the option to accept solderability defects outside their established critical shall be no solder bridging between any termination area and any other metallization not connected to it by design. Inthe event that the solder dipping causes bridging, the test shall not be considered a failure provided that a local application ofheat ( , gas, soldering iron, or redipping) results in solder pullback and no wetting of the dielectric area as indicated bymicroscopic examination. The area of the surface to be tested shall be as specified in leaded devices only, the cut portions of the lead which expose lead ends shall not be used for examination and evaluationof the solder coverage of the acceptable and nonacceptable criteria, see figures 2026-1 through exhibiting corrosion and marking degradation shall not be considered solderability failures. Methods 1041and 1022 shall be used to determine compliance for corrosion and marking failure :The area of the surface to be tested as specified in shall be examined. If all views of the tested surfaceshows less than 95 percent coverage, the device shall be considered as a failure. In the case of a dispute,the percentage of coverage with pinholes or voids shall be determined by the actual measurement of thoseareas, as compared to the total Evaluation of wire wrap terminations. The criteria for acceptable solderability percent of the total length of the fillet, between the standard wire wrap and the termination, is tangent to the surfaceof the termination being tested and free from pinholes, voids, porosity, nonwetting or nonuniform flow line where the solder fillet joins with the surface of the termination may occur from the method of solderapplication and is acceptable providing wetting is as specified in a. Evaluation of devices. After solderability testing, the device shall be inspected in accordance with method 2071 and shall complywith the criteria regarding part mark, legibility, corrosion contamination, finish, and foreign material. This requirement is only for devicesthat will be shipped against the purchase order as production units and not a criteria for solderability end Summary. Unless otherwise noted, the following details are to be specified in the individual number of terminations of each part to be tested (see 4.). preparations of the terminations, if applicable (see ). of immersion, if applicable and if other than , if other than specified in composition, flux, and temperature if other than those specified in this of cycles, if other than one or as noted in this document. Where more than one cycle is specified to test theresistance of the device to heat as encountered in multiple solderings, the examinations and measurements required shall bemade at the end of the first cycle and again at the end of the total number of cycles applied. Failure of the device on anyexamination and measurement at either the one-cycle or the end-point shall constitute a failure to meet this to use this chart is set-up for inch ( mm) long the entire circumference of the the lead diameter on the left side of the the diameter of the void on the top of the chart.(Inches)Void ,000111 4010 ,500167 6015 ,000222 8020 , , , , for less than inch ( mm) length = = determine the number of acceptable voids, multiply the number of voids on the chart by A (.03 mm) void on A (.25 mm) diameter lead = 700 leads greater than inch ( mm) in length (see ).FIGURE 2026-1. Solderability evaluation coverage of a .5 inch ( mm), .025 inch ( mm) diameter lead of 10X magnificationUNROLLED VIEWFIGURE 2026-2. Solderability 2026-3. Porosity. FIGURE 2026-4. 2026-5. Pinholes. FIGURE 2026-6. 2026-7. Foreign 2026-8. Illustration of FIGURE 2026-9. Illustration of acceptable terminal. unsolderable 2026-10. Illustration of acceptable FIGURE 2026-11. Illustration of partially solderable stranded wire. solderable strand wire showing incomplete HEAT1. Purpose. This test is to determine the device resistance to the high temperature encountered during Apparatus. Apparatus used for the soldering heat test shall include temperature controlled solder Procedure. The leads of the device shall be immersed for 10 +2, -0 seconds in molten metal, without flux, at a temperature of+260 C 5 C, to a point .062 .031 inch ( .79 mm) from the body, tubulation or stub of the device. One immersion for each of thedevice leads constitutes one cycle. The number of cycles shall be as specified. All leads may be immersed simultaneously at thediscretion of the manufacturer. The devices shall be allowed to return to ambient temperature between cycles. During immersion, careshall be taken to prevent extreme thermal gradients along the device axis; fixtures shall neither heat sink the diode body nor hold theunimmersed lead closer than .5 inch ( mm) from the Summary. The following conditions shall be specified in the detail of cycles (see 3.). after STRENGTHTEST CONDITION A, TENSION1. Purpose. This test is designed to check the capabilities of the device leads, welds and seals to withstand a straight Apparatus. The tension test requires suitable clamps, vise, and hand vise for securing the device and for securing the specifiedweight to the device lead without lead Procedure. The specified weight shall be applied, without shock, to each lead or terminal. The case of the device shall be held in afixed position. When testing axial lead devices, the device shall be supported, with the leads in a vertical position, by securing one lead toa clamp or vise. With a hand vise or equivalent, the specified weight, including the attaching device, shall be fastened to the lower leadfor the time specified. Each lead shall be fastened as close to its end as practicable. When examined using 10X magnification afterremoval of the stress, any evidence of breakage (other than meniscus), loosening, or relative motion between the terminal lead and thedevice body shall be considered a device Summary. The following details shall be specified in the individual specification:a. Weight to be attached to lead (see 3).b. Length of time weight is to be attached (see 3).c. Measurements to be made after this CONDITION D1, LEAD OR TERMINAL TORQUE1. Purpose. This test is designed to check device leads and seals for their resistance to twisting Apparatus. The torque test requires suitable clamps and fixtures and a torsion wrench or other suitable method of applying thespecified torque without lead Procedure. The body of the device shall be securely clamped, with a suitable fixture, and the specified torque shall be applied to theportion of the terminal nearest the seal for the specified time. The specified torque shall be applied, without shock, about the device torque shall be applied between the lead or terminal and the case in a direction with tends to cause loosening of the lead or UHF and microwave diodes. Unless otherwise specified, a torque of pound-inches (.17 newton-meter) about the diode axisshall be applied for the specified time, without shock, between the terminals, and in a direction which tends to cause loosening of theterminals. The manufacturer's recommendation shall be allowed in the method Examination under magnification. When examined using 10X magnification after removal of the stress, any evidence of breakage(other than meniscus), loosening, or relative motion between the terminal lead and the device body shall be considered a device Summary. The following conditions shall be specified in the detail amount of torque to be applied (see ). of time torque is to be applied (see ). to be made after of 3MIL-STD-750DTEST CONDITION D2, STUD TORQUE1. Purpose. This test is designed to check the resistance of the device with threaded mounting stud to the stress caused bytightening the device when Apparatus. The torque test requires suitable clamps and fixtures and a torsion wrench or suitable method of applying the Procedure. The device shall be clamped by its body or flange. A flat steel washer of a thickness equal to 6-thread pitches of thestud being tested and a class 2 fit steel nut shall be assembled in that order on the stud, with all parts clean and dry. The specifiedtorque shall be applied for the specified length of time without shock to the nut. The nut and washer shall then be disassembled from thedevice, and the device then examined for compliance with the Failure. The device shall be considered a failure stud stud exhibits elongation greater than one-half of one-thread device exhibits obvious visual mechanical deformations, such as:(1)Stripping of threads,(2)Deformation of mounting seat, and(3)Bending of fails the specified post-test and point Summary. The following conditions shall be specified in the detail amount of torque to be applied (see 3). of time torque is to be applied (see 3). to be made after CONDITION E, LEAD FATIGUE1. Purpose. This test is to check the resistance of the device leads to metal Apparatus. The lead-fatigue test shall be made using the specified weight and with suitable clamping or attaching Procedure. Where applicable, two leads on each device shall be tested. The leads shall be selected in a cyclical manner (regularrecurring), when applicable; that is, leads number 1 and 2 on the first device, number 2 and 3 on the second device. Unless otherwisespecified, a weight of 8 ounces (225 15 grams) shall be applied to each lead for three 90 5 degrees arcs of the case. An arc isdefined as the movement of the case, without torsion, to a position perpendicular to the pull axis and return to normal. All arcs on a singlelead shall be made in the same direction and in the same plane without lead restriction. One bending cycle shall be completed in from 2to 5 seconds. Any glass fracture (other than meniscus) or broken lead shall be considered a Summary. The following conditions shall be specified in the detail to be attached to the lead, if other than 8 ounces (225 15 grams) (see 3.). of arcs, if other than three (see 3.). to be made after this CONDITION F, BENDING STRESS1. Purpose. This test is made to check the quality of the leads, lead welds, and glass-to-metal seals of the Apparatus. Bending-stress tests shall be made using attaching devices, such as suitable clamps or other supports forstud-mounted Method A (for cylindrical devices). With one contact of the device held in a suitable clamp, the specified force shall be applied,without shock, at right angles to the reference axis of the device, as near the top of the opposite contact or tubulation as Method B (for stud-mounted devices). The device shall be securely fastened, with its reference axis in a horizontal position, byscrewing the stud into a suitable support. With a hand vise, or equivalent, the specified weight shall be suspended from the hold in thelug for the length of time Failure criteria. When examined using 10X magnification after removal of the stress, any evidence of breakage (other thanmeniscus), loosening, or relative motion between the terminal lead and the device body shall be considered a Summary. The following conditions shall be specified in the detail preparations or conditions, if to be attached to lead (see 3.). method (see and ). of time weight is to be made after 2037BOND STRENGTH1. Purpose. The purpose of this test is to measure bond strengths to determine compliance with specified requirements of theapplicable detail specification. This test may be applied to wire-to-die or clip-to-die bond, wire-to-package lead bond, or thewire-to-substrate bond inside the package of wire or clip connected discrete devices bonded by soldering, thermocompression, ultrasonicor related Apparatus. The apparatus for this test shall consist of suitable equipment for applying the specified force required to cause bondfailure. A measurement of the applied stress in grams force (gf) at the point of failure shall be provided by equipment capable ofmeasuring stresses up to and including 10 gf with an accuracy of gf, stresses between 10 and 50 gf with an accuracy of gf,and stresses exceeding 50 gf with an accuracy of 5 percent of indicated Procedure. The test shall be conducted using the test conditions specified. All bond pulls shall be counted and the specifiedsampling, acceptance and added sample provisions shall be observed, as applicable. Unless otherwise specified, the sample planspecified for the bond strength test shall determine the minimum sample size in terms of the minimum number of pulls to beaccomplished rather than the number of complete devices in the sample ( , wires for test condition A, bonds for test condition B, andclips for test condition C). Where there is any adhesive, encapsulant, or other material used on the die to increase the apparent bondstrength, the bond strength test shall be performed prior to application or, for post seal tests, the material shall be removed. Unlessnondestructive limits are specified, all bond pulls shall be to Test Test condition A: Wire pull, double bond. This test is normally employed for internal bonds at the die or substrate and the leadposts of discrete devices. Under this condition, both bonds are tested simultaneously by inserting a hook under the lead wire and, withthe device clamped, applying the pulling force at mid-point of the wire span. The force shall be applied in the upward direction tending tocause a lift-off separation of the bond from the die and within 5q of perpendicular to: (1) the plane of the die or substrate or, (2) to astraight line between the two bonds. When a failure occurs, the force causing the failure and the failure category shall be Test condition B: Wire pull, single bond (not recommended for wire diameters less than .005 inch ( mm)). This test isemployed when it is desired to test the wire bonds separately at the die or substrate and lead post or when, due to device construction,condition A is inappropriate. Product acceptance is based on testing an equal number of both bonds. When testing die and post bondsseparately, the wire shall be cut to provide two ends accessible for pull testing both die and post bonds. In the case of short wire runs, itmay be necessary to cut the wire close to one termination in order to allow pull at the opposite termination. The free end of the wire shallbe gripped in a suitable device and simple pulling action applied. When the wire exits from the top of the die bond (ball or nailheadbonds), the force shall be applied in a direction that is within 5q of normal to the surface of the die or substrate. When the wire exits fromthe side of the bond (die or lead post), the force shall be applied at an angle equal to or greater than 45q to the surface of the die. Whenfailure occurs, the force causing the failure and failure category shall be Test condition C: Clip pull. This test is employed for internal clips at the die or substrate and the lead posts of discrete pull is applied by inserting a hook under the clip as close to the die attachment point as practical with the device clamped and thepulling force applied approximately in a direction within 5q of normal to the die or substrate. When a failure occurs, the force causing thefailure and the failure category shall be Failure criteria. Any bond pull which results in a separation under an applied stress less than that indicated in table as therequired minimum bond strength for the indicated test condition, composition, and construction shall constitute a Failure 20371 of Failure categories for wire bonds. Failure categories for wire bonds are as break at neckdown point (reduction of cross section due to bonding process). break at point other than in bond (interface between wire and metallization at die). in bond (interface between wire and plating or metallization) at package post, substrate, or other than at metallization from metallization or plating from substrate or package of of Failure categories for clips. Failure categories for clip are as in bond (interface between clip and metallization) at metallization at of clip from package of stress required to achieve separation and the category of the separation or failure shall be Procedure in the event of production sampling failure (unencapsulated devices). If a sample contains more than the allowednumber of defects, the machine(s) from which the sample was taken shall not be allowed to produce additional JAN product until asample has been tested and passed. All devices bonded on the machine(s) that produced the defective(s) since the last acceptablesample inspection will either be rejected or subjected to a 100 percent non-destructive bond pull at a force of one-half the minimumspecified bond pull limit for the particular size wire (see table 2037-I or figure 2037-1). A non-destructive pull force of X - 30 V/2 may besubstituted for this value provided V X. The statistical data for this shall be obtained from actual pull data from the last fullacceptable days production. X is the average pull strength and V is the standard deviation. If percent pure aluminum annealedwire is used, the divisor in the equation shall be changed to three and the sentence above will then read "one-third the minimum specifiedbond pull limit." This procedure shall not be used if the defectives resulted from die fracture since this may indicate damage to the diewhich cannot be screened by non-destructive Summary. The following details shall be specified in the detail condition letter (see 3.). bond strength, if other than as specified in or details of required strength distributions, if or number and selection of bond pulls to be tested on each device, and number of devices, if other than for reporting of separation forces and failure categories, when applicable (see ). SUPERSEDES PAGE 2 OF MIL-STD-750DMETHOD 20372MIL-STD-750DTABLE 2037-1. Minimum bond strength. || Wire|| Minimum bond strength||| composition|| (grams force) 1/|| Test| and| Construction| || condition| diameter| 3/||||| inches 2/|| Preseal| Post seal 4/|| | | | | |||||||| A| Au | Wire| | |||||||| A| A1 | Wire| | ||| Au || | |||||||| A| A1 | Wire| | ||| Au || | |||||||| A| A1 | Wire| | ||| Au || | |||||||| A| A1 | Wire| | ||| Au || | |||||||| A| A1 | Wire| | ||| Au || | |||||||| A| A1 | Wire| | |||||||| A| A1 | Wire| | |||||||| A| A1 | Wire| | |||||||| A| A1 | Wire| | |||||||| C|| Clips| | || | | | | |1/For test condition B, the bond strength limit shall be 75 percent of that required for testcondition wire diameters not listed above, use the curves of figures 2037-1 and 2037-2 todetermine the pull ribbon wire, use the equivalent round wire diameter which gives the samecross-sectional area as the ribbon wire being seal tests to be performed following the processing and screening as 20373MIL-STD-750DFIGURE 2037-1. Bond pull 20374MIL-STD-750DFIGURE 2037-2. Bond pull limits - 20375/6MIL-STD-750DMETHOD FATIGUE1. Purpose. The purpose of this test is to determine the effect on the device of vibration in the frequency range Procedure. The device shall be rigidly fastened on the vibration platform and the leads or cables adequately secured. The deviceshall then be subjected to a sample harmonic motion in the range of 60 20 Hz, with a constant peak acceleration of 20 g minimum. Thevibration shall be applied for 32 8 hours, minimum, in each of the orientations X, Y, and Z for a total of 96 hours, Summary. The measurements after test shall be specified in the detail NOISE1. Purpose. The purpose of this test is to measure the amount of electrical noise produced by the device under Procedure. The device and its leads shall be rigidly fastened on the vibration platform and the leads or cables adequately device shall be vibrated with simple harmonic motion with a constant peak acceleration of 20 g minimum. The vibration frequencyshall be varied approximately logarithmically between 100 and 2,000 Hz. The entire frequency range shall be traversed is not less thanfour minutes for each cycle. This cycle shall be performed once in each of the orientations X1, Y1, and Z1 (total of 3 times), so that themotion shall be applied for a total period of approximately 12 minutes. The specified voltages and currents shall be applied in the testcircuit. The maximum noise-output voltage across the specified load resistance during traverse shall be measured with anaverage-responding root-means-square (rms) calibrated high impedance voltmeter. The meter shall measure, with an error of not morethan 3 percent, the rms value of a sine-wave voltage at 2,000 Hz. The characteristic of the meter over a bandwidth of 20 to 20,000 Hzshall be 1 decibel (dB) of the value at 2,000 Hz, with an attenuation rate below 20 and above 20,000 Hz of 6 2 dB per octave. Themaximum inherent noise in the circuit shall be at least 10 dB, below the specified noise-output Summary. The following conditions shall be specified in the detail voltages and currents (see 2.). resistance (see 2.). test voltage IMPACT NOISE DETECTION (PIND) TEST1. Purpose. The purpose of this test is to detect loose particles inside a device cavity. The test provides a nondestructive means ofidentifying those devices containing particles of sufficient mass that, upon impact with the case, excite the Apparatus. The equipment required for the PIND test shall consist of the following (or equivalent) threshold detector to detect particle noise voltage exceeding a preset threshold of the absolute value of 20 1 mV peakreference to system vibration shaker and driver assembly capable of providing essentially sinusoidal motion to the DUT at:(1)Condition A: 20 g's peak at 40 to 250 Hz.(2)Condition B: 10 g's peak at 60 Hz transducer, calibrated to a peak sensitivity of 3 dB in regards to one volt per microbar at a point within thefrequency of 150 to 160 sensitivity test unit (STU) (see figure 2052-1) for periodic assessment of the PIND system performance. The STU shallconsist of a transducer with the same tolerances as the PIND transducer and a circuit to excite the transducer with a 250microvolt 20 percent pulse. The STU shall produce a pulse of about 20 mV peak on the oscilloscope when the transducer iscoupled to the PIND transducer with attachment electronics, consisting of an amplifier with a gain of 60 2 dB centered at the frequency of peak sensitivity of the PINDtransducer. The noise at the output of the amplifier shall not exceed 10 mV medium. The attachment medium used to attach the DUT to the PIND transducer shall be the same attachmentmedium as used for the STU mechanism or tool capable of imparting shock pulses of 1,000 200 g's peak to the DUT. The duration of the mainshock shall not exceed 100 Ps. If an integral co-test shock system is used the shaker vibration may be interrupted orperturbed for period of time not to exceed 250 ms from initiation of the last shock pulse in the sequence. The co-test durationshall be measured at the 50 5 percent Test equipment setup. Shaker drive frequency and amplitude shall be adjusted to the specified conditions. The shock pulse shallbe adjusted to provide 1,000 200 g's peak to the Test equipment checkout. The test equipment checkout shall be performed a minimum of one time per operation shift. Failure ofthe system to meet checkout requirements shall require retest of all devices tested subsequent to the last successful system of Shaker drive system checkout. The drive system shall achieve the shaker frequency and the shaker amplitude specified. Thedrive system shall be calibrated so that the frequency settings are within 8 percent and the amplitude vibration setting are within 10percent of the nominal values. If a visual displacement monitor is affixed to the transducer, it may be used for amplitudes between .04and .12 inch ( and mm). An accelerometer may be used over the entire range of amplitudes and shall be used below amplitudesof .040 inch ( mm). Detection system checkout. With the shaker deenergized, the STU transducer shall be mounted face-to-face and coaxial withthe PIND transducer using the attachment medium used for testing the devices, prior to attaching any special fixtures. The STU shall beactivated several times to verify low level signal pulse visual and threshold detection on the oscilloscope. Not every application of the STUwill produce the required amplitude. All pulses which are greater than 20 mV shall activate the System noise verification. System noise will appear as a fairly constant band and must not exceed 20 mV peak to peak whenobserved for a period of 30 to 60 Test sequence. The following sequence of operations (a. through i.) constitute one test cycle or pre-test 3 1 co-test 3 1 co-test 3 1 co-test 3 1 or Mounting requirements. Special precautions ( , in mounting, grounding of DUT leads, or grounding of test operator) shall betaken as necessary to prevent electrostatic damage to the part types will mount directly to the transducer via the attachment medium. Parts shall be mounted with the largest flatsurface against the transducer at the center or axis of the transducer for maximum sensitivity. Where more than one large surfaceexists, the one that is the thinnest in section or has the most uniform thickness shall be mounted toward the transducer, , flatpacks are mounted top down against the transducer. Small axial-lead, right circular cylindrical parts are mounted with their axishorizontal and the side of the cylinder against the transducer. Parts with unusual shapes may require special fixtures. Studpackages shall utilize a cylindrical fixture with a non-thru hole such that the bottom of the fixture is solid. The inner hole diametershall be minimized and the fixture diameter shall be greater than the hex flat dimension. Such fixtures shall have the followingproperties:(1)Low mass.(2)High acoustic transmission (aluminum alloy 7075 works well).(3)Full transducer surface contact, especially at the center.(4)Maximum practical surface contact with test part.(5)No moving parts.(6)Suitable for attachment medium Test monitoring. Each test cycle (see ) shall be continuously monitored, except for the period during co-test shocks and 250ms maximum after the shocks. Particle indications can occur in one or any combination of the three detection systems as indication of high frequency spikes which exceed the normal constant background white noise indication of clicks, pops, or rattling which is different from the constant background noise present with no DUT on detection shall be indicated by the lighting of a lamp or by deflection of the secondary oscilloscope Failure criteria. Any noise bursts as detected by any of the three detection systems exclusive of background noise, except thosecaused by the shock blows, during the monitoring periods shall be cause for rejection of the device. Rejects shall not be retested exceptfor retest of all devices in the event of test system failure. If additional cycles of testing on a lot are specified, the entire test procedure(equipment setup and checkout mounting, vibration, and co-shocking) shall be repeated for each retest cycle. Reject devices from eachtest cycle shall be removed from the lot and shall not be retested in subsequent lot Summary. The following details shall be specified in the applicable detail condition letter A or acceptance/rejection criteria (if applicable). number of test cycles, if other than shock level and co-test shock level, if other than switch: Mechanically quiet, fast make, gold contacts. T2 SM4microswitch. 2. Resistance tolerance five percent noninductive. 3. Voltage source can be a standard dry cell. 4. The coupled transducers must be coaxial during test. 5. Voltage output to STU transducer 250 microvolts, 20 2052-1. Typical 2052-2. Package height versus test frequency for 20 g's , VARIABLE FREQUENCY1. Purpose. The variable-frequency-vibration test is performed for the purpose of determining the effect on component parts ofvibration in the specified frequency Mounting. The device shall be rigidly fastened on the vibration platform and the leads or cables adequately Amplitude. The device shall be subjected to a constant peak acceleration of 20 g Frequency range. The vibration frequency shall be varied approximately logarithmically between 100 and 2,000 Sweep time and duration. The entire frequency range of 100 to 2,000 Hz and return to 100 Hz shall be traversed in not less thanfour minutes. This cycle shall be performed 4 times in each of the orientations X, Y, and Z (a total of 12 times), so that the motion shallbe applied for a total period of approximately 48 Summary. The measurements after test shall be specified in the detail , VARIABLE FREQUENCY (MONITORED)1. Purpose. This test is performed for the purpose of detecting malfunctions of semiconductor devices during vibration in thespecified frequency range at the specified Mounting. The device shall be rigidly fastened on the vibration platform. Special care is required to ensure position electricalconnection to the device leads to prevent intermittent contacts during vibration. Care must also be exercised to avoid magnetic fields inthe area of the device being Amplitude. The device shall be vibrated with a simple harmonic motion with a constant peak acceleration of 20 g minimum. Theacceleration shall be monitored at a point where the 'g' level is equivalent to that of the support point for the device(s). Frequency range. The vibration shall be varied logarithmically between 100 and 2,000 Sweep time and duration. The entire frequency range of 100 to 2,000 Hz and return to 100 Hz shall be traversed in not less than 8minutes. This frequency range shall be executed at one time in each of the orientations X, Y, and Z (total of 3 times) so that the motionshall be applied for a total of 24 minutes minimum. Interruptions are permitted provided the requirements for rate of change and testduration are met. Completion of vibration within any separate frequency band is permissible before going on to the next Measurements. With the specified dc voltages and currents applied, the semiconductor device shall be monitored continuously,during the vibration period, for intermittent opens and shorts. The monitoring equipment shall be capable of detecting voltage or currentchanges of the duration and magnitude specified on the individual specification. In addition, the equipment shall utilize apositive-indication "go-no go" technique or a recorded trace. Equipment requiring continuous visual monitoring, such as an oscilloscope,shall not be Summary. The following conditions shall be specified in the detail test duration and magnitude of the voltage or current 2066PHYSICAL DIMENSIONS1. Purpose. The purpose of this examination is to check the physical dimensions of the Apparatus. Equipment used in this examination shall be capable of demonstrating conformance to the requirements of theindividual Procedure. The semiconductor device shall be examined to verify that the physical dimensions are as specified in the Summary. The dimensions which are capable of physically describing the device shall be specified in the detail 20661/2MIL-STD-750DMETHOD 2068EXTERNAL VISUAL FOR NONTRANSPARENT GLASS-ENCASED,DOUBLE PLUG, NONCAVITY AXIAL LEADED DIODES1. Purpose. The purpose of this examination is to visually inspect glass-encased, double plug, noncavity, axial leaded devices forcracks which may affect the integrity of the hermetic Apparatus. A binocular microscope with a magnification of 10X to 20X and sufficient lighting for visual inspection of the glass Procedure. The examination shall be performed prior to any body coating. The devices shall be examined under a magnification of10X to 20X for evidence of glass body Failure criteria. Any device exhibiting cracks in the body glass shall be rejected. Cracks or chipouts in the meniscus area at eitherend of the body are not cause for 20681/2MIL-STD-750DMETHOD VISUAL, POWER MOSFET'S1. Purpose. The purpose of this inspection is to verify the construction and quality of workmanship in the assembly process to thepoint of pre-cap inspection. These various inspections and tests are intended to verify compliance with the requirements of the applicabledetail Apparatus. The apparatus for this inspection shall consist of the equipment capable of the specified magnification(s). fixturing for handling the devices being inspected without causing covered storage and transportation containers to protect devices from mechanical damage andenvironmental visual standards ( , drawings, photographs) necessary to enable the inspector to make objective decisionsas to the acceptability of devices being General. The devices shall be examined in a suitable sequence of observations with the specified magnification range todetermine compliance with the requirements of this document and the applicable detail of inspection. The order in which criteria are presented is not a required order of inspection and may be varied atthe discretion of the control. Within the time interval between visual inspection and preparation for sealing, devices shall be stored in acontrolled environment (an environment in which air-borne particles and relative humidity are controlled). The use of a positivepressure inert gas environment, such as dry nitrogen, shall satisfy the requirement of storing in a controlled a cleaning operation is performed prior to sealing, devices inspected in accordance with this specification shall beinspected in a class 100,000 environment in accordance with FED-STD-209. The maximum allowable relative humidity shallnot exceed 65 percent. Devices shall be in clean covered containers when transferred through any uncontrolled Low magnification inspection shall be performed with either a monocular, binocular or stereo microscope andthe inspection performed with any appropriate angle, with the device under suitable illumination. High magnification may beused to verify a discrepancy which has first been noted at low magnification.(1)High magnification inspection shall be performed within the range of 100X to 400X.(2)Low magnification shall be performed within the range of 30X to Bonding inspection (low magnification). This inspection and criteria shall be the required inspection for the bond type(s) andlocation(s) to which they are applicable when viewed from above (see figures 2069-1 and 2069-2). (Wire tail is not considered part of thebond when determining physical bond dimensions.) No device shall be acceptable which exhibits any of the following Gold ball ball bonds where the ball bond diameter is less than times or greater than times the bonding wire ball bonds where the wire exit is not completely within the periphery of the of ball bonds where the exiting wire is not within boundaries of the bonding visible intermetallic formation at the periphery of any gold ball Wedge wedge bonds that are less than times or greater than times the wire diameter in width, or areless than times or greater than times the wire diameter in length, before cutoff, as viewed from wedge bonds that are less than times or greater than times the wire diameter in width or are lessthan times or greater than times the wire diameter in Tailless bonds (crescent). bonds that are less than times or greater than times the wire diameter in width, or are less than times orgreater than times the wire diameter in bonds where the bond impression does not cover the entire width of the General (gold ball, wedge and tailless). As viewed from above, no device shall be acceptable which exhibits any of the on the die where less than 75 percent of the bond is within the unglassivated bonding pad area (except where due togeometry, the bonding pad is smaller than the bond, the criteria shall be 50 percent). bond tails that extend over and make contact with any metallization not covered by glassivation and not connected to bond tails that exceed two wire diameters in length at the die bonding pad or four wire diameters in length at the packageor on the package post that are not bonded entirely on the flat surface of the post bond on top of another bond, bond wire tail, or residual segment of lead wire. An ultrasonic wedge bond alongside aprevious bond where the observable width of the first bond is reduced less than .25 mil is considered placed so that the separation between bond and adjacent unglassivated die metallization not connected to it, is lessthan bonds where less than 50 percent of the bond is located within an area that is free of eutectic Internal lead wires. This inspection and criteria shall be required inspection for the location(s) to which they are applicable whenviewed from above. No device shall be acceptable that exhibits any of the following wire that comes closer than one wire diameter to unglassivated operating metallization, another wire (common wiresexcluded), package post, unpassivated die area of opposite polarity, or any portion of the package of opposite polarityincluding the plane of the lid to be attached (except by design, but in no case should the separation be less than mil).(Within a mil spherical radial distance from the perimeter of the bond on the die surface, the separation shall be greaterthan mil.) , tears, bends, cuts, crimps, scoring, or neckdown in any wire that reduces the wire diameter by more than 25 percent,except in bond deformation or extra lead lifting or tearing at interface of pad and wire which runs from die bonding pad to package post and has no arc or stress which cross other wires, except common connectors, except by design, in which case the clearance shall be (s) not in accordance with bonding diagram (unless allowed in design documentation, for tuning purposes). wires (an unintended sharp bend) with an interior angle of less than 90q or twisted wires to an extent that stress (ball bonded devices) not within 10q of the perpendicular to the surface of the chip for a distance of greater than milbefore bending toward the package post or other termination Package conditions (low magnification). No device shall be acceptable which exhibits any of the following Foreign material on die surface. All foreign material or particles may be blown off with a nominal gas blow (approximately 20psig) or removed with a soft camel hair brush. The device shall then be inspected for the following attached conductive particles (conductive particles which are attached by less than one-half of their largestdimension) that are large enough to bridge the narrowest unglassivated active metal spacing (silicon chips or any opaquematerial shall be included as conductive particles). droplets, chemical stains, or photoresist on the die surface that bridge any combination of unglassivated metallization orbare silicon areas, except for unused on the surface of the die that covers more than 25 percent of a bonding pad area (or interferes with bonding) or thatbridges any combination of unglassivated metallization or bare silicon areas, except for unused Die to header mounting material which is not visible around at least three sides or 75 percent of the die perimeter. Wettingcriteria is not required if the devices pass an approved die attached evaluation balling of the die mounting material which does not exhibit a fillet when viewed from flaking of the die mounting die mounting material which extends onto the die surface or extends vertically above the top surface of the die andinterferes with Die die which is not oriented or located in accordance with the applicable assembly drawing of the is visibly tipped or tilted (more than 10q) with respect to the die attach Internal package defects (low magnification inspection) (applicable to headers, bases, caps, and lids). As an alternative to 100percent visual inspection of lids and caps in accordance with the criteria of , the lids or caps may be subjected to a suitablecleaning process and quality verification procedure approved by the qualifying activity, provided the lids or caps are subsequently held in acontrolled environment until capping or preparation for header or post plating which is blistered, flaked, cracked, or any combination conductive particle which is attached by less than one-half of the longest bubble or a series of interconnecting bubbles in the glass surrounding the pins which are more than one-half the distancebetween the pin and body or posts which are severely glass, die, or other material greater than one mil in its major dimension which adheres to the flange or side of the headerand would impair stain, varnish, or header discoloration which appears to extend under a die bond or wire isolated stud packages:(1)Any defect or abnormality causing the designed isolating paths between the metal island to be reduced to lessthan 50 percent of the design separation.(2) A crack or chip-out in the Carrier defects (( , BeO, alumina) substrate). chip-out in the carrier metallization which is smeared or is obviously not uniform in metallization design pattern to the extent that there is lessthan 50 percent of the original design separation, or mil whichever is less, between operating pads, paths, lid mountingmetallization, edges, or any combination crack in the BeO or operating metallization that would affect hermetic seal or die mounting metallization. (Tooling marksor cold form interface lines are not cracks and are not cause for rejection.) metallization lifting, peeling, or blistering (on the carrier surface). attached conductive foreign material which bridges any combination of metallization paths, leads, or active scratch or void in the metallization which exposes the substrate anywhere along its length and leaves less than 75 percentof the original metal width undisturbed. NOTE:Occasionally package metallization is intentionally burnished or scratched, in areas which require wire bond attachment,to improve surface bondability; such conditions are not cause for rejection. Burnished or scratched areas must satisfythe criteria of scratches in carrier metallization due to abuse in handling or staple, bridge, or clip with solder joint which exhibits less than 50 percent wetting around the section that is attached tothe header post(s) which are not perpendicular within 10q of the horizontal plane of the lead attach eutectic or solder which extends across greater than 50 percent of the design separation gap betweenmetallization Presence of extraneous matter. Extraneous matter (foreign particles) shall include, but not be limited foreign particle, loose or attached, greater than .003 inch ( mm) or of any lesser size which is sufficient to bridgenonconnected conducting elements of the wire tail extending beyond its normal end by more than two diameters at the semiconductor die pad or by more than fourwire diameters at the package post (see figure 2069-3). burr on a post (header lead) greater than .003 inch ( mm) in its major dimension or of such configuration that it maybreak semiconductor die bonding material buildup. A semiconductor die shall be mounted and bonded so that it is nottilted more than 10q from mounting surface. The bonding agent that accumulates around the perimeter of the semiconductordie and touches the side of the semiconductor die shall not accumulate to a thickness greater than that of the semiconductordie (see figures 2069-4 and 2069-5). Where the bonding agent is built up but is not touching the semiconductor die, the buildup shall not be greater than twice the thickness of the semiconductor die. There shall be no excess semiconductor diebonding material in contact with the active surface of the semiconductor die or any lead or post, or separated from the mainbonding material area (see figure 2069-6). on the header or posts or anywhere inside the ball bonds anywhere inside case, except for attached bond residue when rebonding is Summary. The following details shall be specified in the applicable detail or additions to the inspection applicable, any conflicts with approved circuit design topology or applicable; gauges, drawings, and photographs that are to be used as standards for operator applicable, specific Tailless or : 1. D d W d D (width). 2. D d L d D (length).B. ThermocompressionNOTES: NOTES: 1. D d W d D (width)1. D d W d D (width) 2. D d L d D (length)2. D d L d D (length)FIGURE 2069-1. Bond 2069-2. Lifted/torn 2069-3. Acceptable and unacceptable voids and excessive 2069-4. Acceptable and unacceptable bonding material 2069-5. Extraneous bonding material 2069-6. Acceptable and unacceptable excess VISUALMICROWAVE DISCRETE AND MULTICHIP TRANSISTORS1. Purpose. The purpose of this inspection is to verify the construction and quality of workmanship in wafer, wafer dc testing, dieinspection, and assembly processes to the point of pre-cap inspection. These various inspections and tests are intended to detect andremove transistor die with defects that could lead to device failure during application and to verify compliance with the requirements of theapplicable detail Apparatus. The apparatus for this inspection shall consist of the equipment capable of the specified magnifications, and both normal incident and darkfield fixturing for handling the devices being inspected without causing covered storage and transportation containers to protect devices from mechanical damage and visual standards ( , drawings, photographs) necessary to enable the inspector to make objective decisions as to theacceptability of devices being General. The devices shall be examined in a suitable sequence of observations with the specified magnification range todetermine compliance with the requirements of this document and the applicable detail of inspection. The order in which criteria are presented is not a required order of inspection and may be varied atthe discretion of the control. Within the time interval between visual inspection and preparation for sealing, devices shall be stored in acontrolled environment (an environment in which air-borne particles and relative humidity are controlled). The use of a positivepressure inert gas environment, such as dry nitrogen, shall satisfy the requirement of storing in a controlled a cleaning operation is performed prior to sealing, devices inspected in accordance with this specification shall beinspected in a class 100,000 environment in accordance with FED-STD-209. The maximum allowable relative humidity shallnot exceed 65 percent. Devices shall be in clean covered containers when transferred through any uncontrolled High magnification inspection shall be performed perpendicular to the die surface with normal incident ordarkfield illumination as required. Low magnification inspection shall be performed with either a monocular, binocular, orstereo microscope and the inspection performed with any appropriate angle, with the device under suitable illumination. Highmagnification may be used to verify a discrepancy which has first been noted at low magnification.(1)High magnification inspection shall be performed within the range of 60X to 200X.(2)Low magnification shall be performed within the range of 30X to 60X.(3)Wafer inspection shall be performed within the range of 100X to 1,200X, however the lowest magnification used must behigh enough to allow this inspection to be reject criteria: Unless otherwise specified, reject if the defect is present in 25 percent of any one cell or in 10 percentof the entire 2070-5 through 2070-9 illustrate different geometries used in fabricating microwave discrete of Wafer inspection (may be performed any time after metallization). Each wafer in a run shall be inspected by examining patterns ineach of the four quadrants and near the center of the wafer. The sample shall be determined in accordance with table 2070-I. Sample sizes and rejects. 1/ 2/ ||||| Die on a wafer| Shorts due to bridging | All others || |Sample size |Reject number |Sample size |Reject number |||||||| <501| 20| 5| 50| 4|||||||| 501 to 1,200| 32| 8| 80| 6|||||||| 1,201 to 3,200| 50| 13| 125| 8|||||||| 3,201 to 10,000| 80| 20| 200| 11|| | | | | |1/When inspection is performed prior to probing, the lot size shall bedetermined by the number of die on the wafer. When inspection is performedafter probing, the lot size shall be determined by the number of goodelectrical the manufacturer's option, electrically good die from a rejected wafermay be inspected 100 percent for the defect which caused the wafer rejection,provided the same or greater magnification is Metallization inspection. Unless otherwise specified, the 25 percent of a cell and 10 percent of a die reject conditions apply). Nodie shall be acceptable which exhibits any of the following misalignment so that there is less than 75 percent coverage of the ohmic contact window that has less than a continuous 50 percent of its perimeter covered by :Metal coverage is not required at the far dielectric steps of the end base contacts under basemetal finger must cover 50 percent of the contact that lies over the enhancement bridging, between two normally unconnected metallization paths, which reduces the design separation to lessthan 50 percent or mil whichever is corrosion. Any metallization which shows evidence of adherence. Any metallization which has lifted, peeled, or : Do not reject for missing or defective run around metal (run around metal is nonactive metal used for probingpurposes with multicell devices).METHOD Glassivation and silicon nitride defects. (Unless otherwise specified, the 25 percent of a cell and 10 percent of a die rejectconditions apply). No die shall be acceptable which exhibits any of the following crazing that prohibits the detection of voids or scratches during subsequent inspection or that covers more than 25percent of the die glassivation which has or more adjacent active metallization paths which are not covered by glassivation, except by areas at the edge of bonding pads which expose which covers more than 25 percent of the designed bonding pad crazing covering more than 25 percent of the die cracks which form closed loops over adjacent metallization Die metallization defects (high magnification). No die shall be acceptable which exhibits any of the following Metallization scratches and voids exposing underlying material (see figure 2070-1). Unless otherwise specified, the 25 percentof a cell and 10 percent of a die conditions scratch or void that severs the innermost metallized guard die containing a void in the metallization at the bonding pad covering more than 25 percent of the pad area (see figure2070-1). all devices with expanded contacts. A scratch whether or not underlying material is exposed or a void, which leaves lessthan 50 percent undisturbed metal width in the metal connecting the pad and the contact expanded contacts with more than 10 contact regions. A scratch or void extending across more than 50 percent of thefirst half of any contact region (beginning at the bonding area) in more than 10 percent of the contact expanded contacts with less than 10 contact regions. A scratch or void in the contact area which isolates more than 10percent of the contact probing. Criteria contained in shall apply as limitation on probing Scribing and die defects (high magnification). No device shall be acceptable which exhibits any of the following defects (see figure2070-2) by design, less than mil passivation visible between active metallization or bond pad periphery and the edge of chip-out or crack in the active crack which exceeds mils in length beyond the scribe grid or line that points toward active metallization or an chip-out that extends to within mil of an active area or to within 50 percent of the design spacing, whichever is crack or chip-out that extends under any active if more than 25 percent of a depletion ring is missing. A depletion ring encompasses an individual cell. An annularring encompasses the entire die. A true annular ring will be the same color as the Bonding inspection (low magnification). This inspection and criteria shall be the required inspection for the bond types andlocations to which they are applicable when viewed from above (see figures 2070-3 and 2070-4). (Wire tail is not considered part of thebond when determining physical bond dimensions.) No device shall be acceptable which exhibits any of the following Gold ball ball bonds where the ball bond diameter is less than times or greater than times the bonding wire ball bonds where the wire exit is not completely within the periphery of the ball bonds where the exiting wire is not within boundaries of the bonding visible intermetallic formation at the periphery of any gold ball Wedge wire: Ultrasonic/thermasonic wedge bonds that are less than times or greater than times the wire diameterin width, or less than times or greater than times the wire diameter in wire: Ultrasonic/thermasonic wedge bonds that are less than times or greater than times the wire diameter inwidth, or less than times or greater than times the wire diameter in wedge bonds that are less than times or greater than times the wire diameter in width or are lessthan times or greater than times the wire diameter in Tailless bonds (crescent). bonds that are less than times or greater than times the wire diameter in width, or are less than times orgreater times the wire diameter in bonds where the bond impression does not cover the entire width of the General (gold ball, wedge, and tailless). As viewed from above, no device shall be acceptable which exhibits any of the on the die where less than 50 percent of the bond is within the unglassivated bonding pad bond tails that extend over and make contact with any metallization not covered by glassivation and not connected to bond tails that exceed two wire diameters in length at the die bonding pad or four wire diameters in length at the packageor on the package post that are not bonded entirely on the flat surface of the post bond on top of another bond, bond wire tail, or residual segment of lead wire. An ultrasonic wedge bond alongside aprevious bond where the observable width of the first bond is reduced less than .25 mil is considered placed so that the separation between bond and adjacent unglassivated die metallization not connected to it is lessthan mil, except if the glass does not exhibit cracking, the separation may be shall be permitted with the following limitations:(1)No scratched, open, or discontinuous metallization paths or conductor patterns shall be repaired by bridging with oraddition of bonding wire or ribbon.(2)All rebonds shall be placed on at least 50 percent undisturbed metal (excluding probe marks that do not expose oxide)and no more than one rebond attempt at any design bond location shall be permitted at any pad or post and no rebondsshall touch an area of exposed oxide caused by lifting metal.(3)The total number of rebond attempts shall be limited to a maximum of 10 percent of the total number of bonds in thedevice. The 10 percent limit on rebonds may be interpreted as the nearest whole number of bonds in the device. Abond shall be defined as a wire to post or wire to bond pad. Bond-offs required to clear the bonder after anunsuccessful first bond attempt need not be considered as rebonds provided they can be identified as bond-offs bybeing made physically away from normal bond areas. The initial bond attempt need not be visible. A replacement ofone wire at one end or an unsuccessful bond attempt at one end of the wire counts as one rebond; a replacement ofwire bonded at both ends, or an unsuccessful bond attempt of a wire already bonded at the other end, counts as bonds where less than 50 percent of the bond is located within an area that is free of eutectic melt. The blush area shallnot be considered part of the eutectic melt (The blush area is defined as the area where a color change can be seen but not achange in surface texture). Internal lead wires. This inspection and criteria shall be required inspection for the locations to which they are applicable whenviewed from above. No device shall be acceptable that exhibits any of the following wire that comes closer than one wire diameter to unglassivated operating metallization, another wire (common wiresexcluded), package post, unpassivated die area of opposite polarity, or any portion of the package of opposite polarityincluding the plane of the lid to be attached (except by design, but in no case should the separation be less than .25 mil).(Within a mil spherical radial distance from the perimeter of the bond on the die surface, the separation shall be greaterthan mil.) , tears, bends, cuts, crimps, scoring, or neckdown in any wire that reduces the wire diameter by more than 25 percent,except in bond deformation or extra lead lifting or tearing at interface of pad and wire which runs from die bonding pad to package post and has no arc or stress which cross other wires, except common connectors, except by design, in which case the clearance shall be not in accordance with bonding diagram (unless allowed in design documentation, for tuning purposes). wires (an unintended sharp bend) with an interior angle of less than 90q or twisted wires to an extent that stress (ball bonded devices) not within 10q of the perpendicular to the surface of the chip for a distance of greater than milbefore bending toward the package post or other termination Package conditions (low magnification). No device shall be acceptable which exhibits any of the following Foreign material on die surface. All foreign material or particles may be blown off with a nominal gas blow (approximately 20 psi(138 kPa)) or removed with a soft camel hair brush. The device shall then be inspected for the following attached conductive particles (conductive particles which are attached by less than one-half of their largestdimension) that are large enough to bridge the narrowest unglassivated active metal spacing (silicon chips or any opaquematerial shall be included as conductive particles). droplets, chemical stains, or photoresist on the die surface that bridge any combination of unglassivated metallization orbare silicon areas, except for unused on the surface of the die that covers more than 25 percent of a bonding pad area (or interferes with bonding) or thatbridges any combination of unglassivated metallization or bare silicon areas, except for unused entrapped opaque material which appears to extend over Die to header mounting material which is not visible around at least three sides or 75 percent of the die perimeter. Wettingcriteria is not required if the devices pass an approved die attached evaluation balling of the die mounting material which does not exhibit a fillet when viewed from flaking of the die mounting die mounting material which extends onto the die surface beyond the scribe zone and comes closer than mil to anyactive area or metallization, or extends vertically above the top surface of the die and interferes with Die die which is not oriented or located in accordance with the applicable assembly drawing of the is visibly tipped or tilted (more than 10q) with respect to the die attach Internal package defects (applicable to headers, bases, caps, and lids). As an alternative to 100 percent visual inspection, thelids or caps may be subjected to a suitable cleaning process and quality verification procedure approved by the qualifying activity,provided the lids or caps are subsequently held in a controlled environment until capping or preparation for header or post plating which is conductive particle which is attached by less than one-half of the longest isolated heat sink packages:(1)Any defect or abnormality causing the designed isolating paths between the metal islands to be reduced to less than 50percent of the design separation or reduced to mil, whichever is less.(2)A crack in the Carrier defects (( , BeO, alumina) substrate). chip-out in the carrier metallization which is smeared or is obviously not uniform in metallization design pattern to the extent that there is lessthan 50 percent of the original design separation, or mil whichever is less, between operating pads, paths, lid mountingmetallization, edges, or any combination crack in the BeO or operating metallization that would affect hermetic seal or die mounting metallization. (Tooling marksor cold form interface lines are not cracks and are not cause for rejection.) metallization lifting, peeling, or blistering (on the carrier surface). attached conductive foreign material which bridges any combination of metallization paths, leads, or active scratch or void in the metallization which exposes the substrate anywhere along its length and leaves less than 75 percentof the original metal width :Occasionally package metallization is intentionally burnished or scratched, in areas which require wire bondattachment, to improve surface bondability; such conditions are not cause for rejection. Burnished or scratchedareas must satisfy the criteria of scratches in carrier metallization due to abuse in handling or staple, bridge, or clip with solder joint which exhibits less than 50 percent wetting around the section that is attached tothe header posts which are not perpendicular within 10q of the horizontal plane of the lead attach eutectic or solder which extends across greater than 50 percent of the design separation gap betweenmetallization Capacitor defects (high magnification). through the metal that extend the length of the metal and expose underlying metallization peeling (except due to bond tail pull). metallization which shows evidence of in the silicon that point toward the metal and are within 1 mil of the metal (except for ground bar portion). within mil of the metal (except for ground bar portion). that has been gouged or probed over 20 percent of a bonding pad area and exposes underlying Mounting material which is not visible around at least three sides or 75 percent of the capacitor perimeter. Wetting criteria isnot required if the devices pass an approved capacitor attach evaluation test. (This inspection is to be performed at lowmagnification.)NOTE:Multiple bonding is allowable for tuning purposes, however initial bond wire shall be completely removed beforerebonding and must be in accordance with design Alignment (This applies to 25 percent of any one cell or 10 percent of any die). Reject any diffusion line which touches anotherdiffusion line, except for contact enhancements, which can touch an active area of the same type. Emitter contacts can touch emitterbase junction but cannot cross. Base contacts must engage 50 percent or more of the contact : Contacts are not Resistors (criteria applies to 25 percent of any one cell or 10 percent of any die. Process level Defect RejectNICR resistorPinchedResistor is less than90 percent of itsintended design is less than75 percent of itsintended design orBridging betweenexcess NICRdiscrete defectsNo visible definitionsMisalignmentContacting less than90 percent of itsintended design less than75 percent of itsintended design etchedResistor is greaterthan 125 percent ofits intended SI resistorPinchedResistor is less than90 percent of itsintended design SI resistorUndercutResistor is lessthan 75 percent ofits intended orBridging betweenexcess poly SIdiscrete lessthan 75 percent ofthe if 25 percent of any one cell or 10 percent of any die exhibits burned or missing NICR resistor. Thin film deposited and patterned usually connecting emitter fingers to emitter feed metal to control current. Itcan also be used as a passive element in RF IC' Poly SI resistors (bevel). Thin film of poly SI is deposited, doped, and patterned usually connecting emitter fingers to emitterfeed metal to control current. It can also be used as passive elements in RF IC' Diffused resistors (contact appearance). A diffused area connecting emitter fingers to emitter feed metal used to control Contacts and diffusion defects (contacts are not diffused). Reject if contacts are less than 50 percent of design on 10 percentof the die. Reject any die that has a discontinuous implant or diffusion line effecting more than 10 percent of the die. A discontinuousline is a line that wanders but does not close on itself. Reject any die where an implant or diffusion fault bridges between two diffuseareas, any two metallized stripes of any combination not intended by design. This must effect greater than 10 percent of the die. Rejectany implant or diffused area that is less than 50 percent of Passivation or oxide defects. This applies to 25 percent of a cell and 10 percent of the die. Reject any active junction notcovered by passivation or glassivation. Reject for absence of passivation or oxide visible at the edge and continuing under themetallization causing a short between the metal and the underlying material (unless by design). Reject for passivation or oxide defectsthat allows bridging between any two metallized Summary. The following details shall be specified in the applicable detail or additions to the inspection applicable, any conflicts with approved circuit design topology or applicable, gauges, drawings, and photographs that are to be used as standards for operator applicable, specific 2070-1. Metallization scratches and voids (expanded contact).METHOD Die with guard Die without guard 2070-2. Cracks and Tailless or :1. D d W d D (width)2. D d L d D (length)B. Wedge. Ultrasonic Thermocompression NOTES: NOTES: 1. D d W d D (width) 1. D d W d D (width) 2. D d L d D (length) 2. D d L d D (length)FIGURE 2070-3. Bond LIFTEDFIGURE 2070-4. Lifted/torn 2070-5. Mesh 2070-5. Mesh geometry - 2070-6. Interdigitated 2070-7. Spine 2070-7. Spine geometry - AND MECHANICAL EVALUATION1. Purpose. The purpose of this examination is to verify the workmanship of hermetically packaged devices. This method shall alsobe utilized to inspect for damage due to handling, assembly, and test of the packaged device. This examination is normally employed atoutgoing inspection within the device manufacturers facility, or as an incoming inspection of the assembled Apparatus. Apparatus used in this test shall be capable of demonstrating device conformance to the applicable requirements of theindividual specification. This includes optical equipment capable of magnification 3X minimum to 10X maximum with a large field of viewsuch as an illuminated ring Procedure. Unless otherwise specified, the device shall be examined under a magnification of 3X minimum. The field of view shallbe sufficiently large to contain the entire device and allow inspection to the criteria listed in Where inspection at a lower magnificationreveals an anomaly, then inspection at a higher magnification (10X maximum) may be performed to determine a disposition is in doubt for any dimensional criteria, that dimension may be measured for Failure criteria. Devices which exhibit any of the following shall be considered Rejects. Device construction (package outline), lead (terminal), identification, markings (content, placement, and legibility), andworkmanship not in accordance with the applicable specification shall be rejected. This includes the misalignment of component parts to the extent that the package outline drawing dimensions are evidence of corrosion or contamination. Discoloration is not sufficient cause for rejection. The presence of leadcarbonate formations in the form of a white/yellow crystalline shall be considered evidence of or bent leads or terminals which precludes their use in the intended finish: Evidence of blistering, or evidence of nonadhesion, peeling, or flaking which exposes underplate or that will cause lead or terminal dimensions to be material (including solder or other metallization) bridging leads or otherwise interfering with the normal application ofthe device. Where adherence of foreign material is in question, devices may be subjected to a clean filtered air stream(suction or expulsion) and then beyond seating plane that will interfere with proper seating of the welds or causing distortion of a flange beyond its normal to a stud (thread damage or bending) which restricts normal in metal lids which precludes their use in the intended , separations, or other openings that are not part of the normal design Tubulation weld: Any fracture or split in the tubulation alignment: Base weld mating surfaces not parallel, or that precludes intended of Failure criteria for lead/terminal seal area of metal can cracks (except meniscus cracks) that extend more than one-half of the distance from the pin to the outer member (seefigure 2071-1). Radial cracks that originate from the outer Circumferential cracks (except meniscus cracks) that extend more than 90q around the seal center (see figure 2071-2).c. Open surface bubble(s) in strings or clusters that exceed two-thirds of the distance between the lead and the package Visible subsurface bubbles that exceed the following:(1)Large bubbles or voids that exceed one-third of the glass sealing area (see figure 2071-3).(2)Single bubble or void that is larger than two-thirds of the distance between the lead and the package wall at the site ofthe inclusion and extends more than one-third of the glass seal depth (see figure 2071-4).(3)Two bubbles in a line totaling more than two-thirds of the distance from pin to case (see figure 2071-5).(4)Interconnecting bubbles greater than two-thirds of the distance between pin and case (see figure 2071-6). as designed, reentrant seals which exhibit non-uniform wicking or negative percent or greater of the radius length from the center of the feedthrough to the edge of the glass meniscus cracks that are not located within one-half of the distance between the lead to the case (see figure 2071-7).The glass meniscus is defined as that area of glass that wicks up the lead or chip-out of ceramic or sealing glass that penetrates the sealing glass deeper than the glass meniscus plane. Exposedbase metal as a result of meniscus chip outs are acceptable if the exposed area is no deeper than inch ( mm) or 50percent of lead diameter, whichever is greater (see figure 2071-8). Failure criteria for ceramic packages. Failure criteria for ceramic packages (see MIL-STD-883, method 2009). Failure criteria for opaque glass body devices. Failure criteria for opaque glass body devices (see method 2068 of MIL-STD-750). Meniscus cracks. Meniscus cracks in axial leaded glass packages are not cause for Summary. The following details shall be specified in the applicable acquisition for markings and the lead (terminal) or pin requirements for materials, design, construction, and requirements, if other than 2071-1. Radial cracks extending more than one-half the distance from pin toouter 2071-2. Circumferential 2071-3. Bubbles in glass exceeding one-third of the sealing 2071-4. Single bubble or 2071-5. Two bubbles in a 2071-6. Interconnecting 2071-7. Meniscus 2071-8. Chip VISUAL TRANSISTOR (PRE-CAP) INSPECTION1. Purpose. The purpose of this inspection is to verify the construction and workmanship of bipolar transistors, field effect transistors(FET), discrete monolithic, multichip, and multijunction devices excluding microwave and selected RF devices. This test will beperformed prior to capping or encapsulation to detect those devices with internal defects that could lead to failures in normal applicationand verify compliance with the requirements of the applicable detail Apparatus. The apparatus for this inspection shall consist of the equipment capable of the specified sources of sufficient intensity to adequately illuminate the devices being fixturing for handling the devices being inspected without causing covered storage and transportation containers to protect devices from mechanical damage and visual standards (drawings and photographs) necessary to enable the inspector to make objective decisions as to theacceptability of the devices being Glassivation. The top layer of transparent insulating material that covers the active circuit area metallization, but excluding Passivation. Silicon oxide, nitride, or other insulating material that is grown or deposited directly on the die prior to the deposition ofany General. The device shall be examined in a suitable sequence of observations within the specified magnification range todetermine compliance with the requirements of the applicable detail specification and the criteria of the specified test condition. If aspecified visual inspection requirement is in conflict with the topology or construction of a specific device design, alternate inspectioncriteria may be included in the detail specification. Any alternate inspection criteria contained in the detail specification shall takeprecedence over the criteria of this test method. Any criteria of this test method intended for a specific device process or technology hasbeen indicated. Where applicable, unused cells shall not be subjected to internal visual of inspection. The order in which criteria are presented is not a required order of examination and may be varied atthe discretion of the manufacturer. Visual criteria specified in , , , and , may be examined prior to dieattachment with reexamination at low or high magnification after die attachment for these criteria. Visual criteria specified and may be examined prior to lead wire bonding without reexamination after control. Within the time interval between visual inspection and preparation for sealing, devices shall be stored in acontrolled environment (one which controls airborne particle count and relative humidity). The use of an inert gasenvironment, such as dry nitrogen shall satisfy the requirements for storing in a controlled environment. Devices examined inaccordance with this test method shall be inspected and stored in a class 100,000 environment, in accordance withFED-STD-209, except that the maximum allowable relative humidity shall not exceed 65 devices are subjected to a high temperature bake (>+100qC) immediately prior to sealing, the humidity control is notrequired. Unless a cleaning operation is performed prior to sealing, devices shall be in covered containers when transferredfrom one controlled environment to of High magnification inspection shall be performed perpendicular to the die surface with normal incidentillumination. Low magnification inspection shall be performed with either a monocular, binocular, or stereo microscope, andthe inspection performed within any appropriate angle, with the device under suitable illumination. The inspection criteria and may be examined at "high magnification" at the manufacturer's option. High power magnification may beused to verify a discrepancy noted at a low Die magnification requirements. ||||| Chip size 1/| High magnification| Low magnification|| | | |||||| 30 mils or less| 100X to 200X| 30X to 50X|||||| 31 to 60 mils| 75X to 150X| 30X to 50X|||||| 61 to 150 mils| 35X to 120X| 10X to 30X|||||| Greater than 150 mils| 25X to 75X| 10X to 30X|| | | |1/ Length of shortest Unless a specific magnification is required by the detail specification, when inspection for product acceptanceor quality verification of the visual requirements herein is conducted subsequent to the manufacturer's successful inspection,the additional inspection may be performed at any magnification specified herein. If sampling is used rather than 100 percentreinspection, reevaluation of lot quality in accordance with the "Reevaluation of lot quality" of MIL-S-19500 shall be If conditional exclusions have been allowed, specific instruction as to the location and conditions for which theexclusion can be applied shall be documented in the assembly inspection Die metallization defects (high magnification). A die which exhibits any of the following defects shall be Metallization, scratches, and voids exposing underlying material (see figure 2072-1). scratch or void that severs the innermost metallized guard die containing a void in the metallization at the bonding pad covering more than 25 percent of the pad devices with nonexpanded contacts and all power devices. Any scratch or void which isolates more than 25 percent of thetotal metallization of an active region from the bonding all devices with expanded contacts. A scratch or void, whether or not underlying material is exposed, which leaves lessthan 50 percent undisturbed metal width in the metal connecting the pad and contact expanded contacts with more than 10 contact regions. A scratch or void extending across more than 50 percent of thefirst half of any contact region (beginning at the bonding area) in more than 10 percent of the contact expanded contacts with less than 10 contact regions. A scratch or void in the contact area which isolates more than 10percent of the metallized area from the bonding Metallization corrosion. Any metallization which shows evidence of Metallization adherence. Any metallization which has lifted, peeled, or Metallization probing. Criteria contained in shall apply as limitations on probing Metallization bridging. Metallization bridging between two normally unconnected metallization paths which reduces theseparation, such that a line of oxide is not visible (no less than mil) when viewed at the prescribed high Metallization by design, contact window that has less than 50 percent of its area covered by continuous metallization path not intended to cover a contact window which is separated from the window by less than by design, any misalignment to the extent that continuous passivation color cannot be seen ( , metallization crossingpassivation). Passivation and diffusion faults (high magnification). A device which exhibits any of the following defects (see figure 2072-2)shall be diffusion fault that allows bridging between any two diffused areas, any two metallization strips, or any such combinationnot intended by passivation fault including pinholes not covered by glassivation that exposes semiconductor material and allows bridgingbetween any two diffused areas, any two metallization strips, or any such combination not intended by intended by design, a diffusion area which is by design, an absence of passivation visible at the edge and continuing under the metallization causing an apparentshort between the metal and the underlying material (closely spaced double or triple lines on the edges of the defect indicatethat it may have sufficient depth to penetrate down to the silicon). by design, any active junction not covered by passivation or by design, a contact window in a diffused area which extends across a Scribing and die defects (high magnification). A device which exhibits any of the following defects (see figure 2072-3) shall by design, less than mil passivation visible between active metallization or bond pad periphery and the edge of chip-out or crack in the active by design, die having attached portions of the active area of another die and which exceeds 10 percent of the area ofthe second crack which exceeds mils in length inside the scribe grid or scribe line that points toward active metallization or activearea and extends into the oxide chip-out that extends to within 1 mil of a crack or chip-out that extends under any active metallization chip-out which extends completely through the guard Bond inspection (low magnification). This inspection and criteria shall be the required inspection for the bond type(s) andlocation(s) to which they are applicable when viewed from above (see figures 2072-4 and 2072-5). Wire tail is not considered part of thebond when determining physical bond dimensions. A device which exhibits any of the following defects shall be Gold ball ball bonds on the die or package post where the ball bond diameter is less than times or greater than times thewire ball bonds where the wire exit is not completely within the periphery of the ball bonds where the existing wire is not within the boundaries of the bonding visible intermetallic formation at the periphery of any gold ball Wedge wedge bonds on the die or package post that are less than times or greater than times the wire diameter inwidth, or are less than times or greater than times the wire diameter in wedge bonds on the die or package post that are less than times or greater than times the wirediameter in width or are less than or greater than times the wire diameter in Tailless bonds (crescent). bonds on the die or package post that are less than times or greater than times the wire diameter in width, orare less than times or greater than times the wire diameter in bonds where the bond impression does not cover the entire width of the General (gold ball, wedge, and tailless). As viewed from above, a device which exhibits any of the following defects shall on the die where less than 75 percent of the bond is within the unglassivated bonding pad area (except where due togeometry, the bonding pad is smaller than the bond, the criteria shall be 50 percent). bond tails that extend over and make contact with any metallization not covered by glassivation and not connected to bond tails that exceed two wire diameters in length at the bonding pad or four wire diameters in length at the on the package post that are not bonded entirely on the flat surface of the post bond on top of another placed so that the separation between bonds and adjacent unglassivated die metallization is less than placed so that the separation between bonds and adjacent glassivated die metallization is less than placed so that the separation between adjacent bonds is less than mil. This criteria does not apply to designswhich employ multiple bond wires in place of a single located where any of the bond is placed on an area containing die preform mounting on conductors by bridging or addition of bonding wire or aluminum wires over mils diameter, the bond width shall not be less than times the wire Internal lead wires (low magnification). This inspection and criteria shall be required inspection for the location(s) to which theyare applicable when viewed from above. A device which exhibits any of the following defects shall be wire that comes closer than two wire diameters or 5 mils, whichever is less, to unglassivated operating metallization,another wire (common wires and pigtails excluded) package post, unpassivated die area, or any portion of the package,including the plane of the lid to be attached. (Within a mil spherical radial distance from the perimeter of the bond on thedie surface, the separation can be mil.) , tears, bonds, cuts, crimps, scoring, or neckdown in any wire that reduces the wire diameter by more than 25 or extra lead lifting or tearing at interface of pad and wire (see figure 2072-5). wire which runs from die bonding pad to package post and has no arc or stress in common connectors, wires which cross other (s) not in accordance with bonding is kinked (unintended sharp bend) with an interior angle of less than 90q or twisted to an extent that stress marks (ball bonded devices) not within 10q of the perpendicular to the surface of the chip for a distance of greater than milbefore bending toward the package post or other termination lead burn at lead post longer than 50 percent of post bow or loop between double bonds at post greater than four times wire Excessive loops, bows, or sags in any wire such that it could short to another wire, to another pad, to another package post, tothe die or touch any portion of the hen clips are used, solder fillets shall encompass at least 50 percent of the clip-to-die and post-to-clip periphery. Thereshall be no deformation or plating defects on the Package conditions (magnification as indicated). A device which exhibits any of the following defects shall be Conductive foreign material on die surface. All foreign material or particles may be blown off with a nominal gas blow(approximately 20 psi (138 kPa)) or removed with a soft camel hair brush. The device shall then be inspected for the following criteria(low magnification) attached foreign particles (conductive particles which are attached by less than one-half of their largest dimension)which are present on the surface of the die that are large enough to bridge the narrowest unglassivated active metal spacing(silicon chips shall be included as conductive particles). foreign particles on the die that bridge two or more metallization paths or semiconductor junctions, or anycombination of metallization or droplets, chemical stains, or photoresist on the die surface that bridge any combinations of unglassivated metal or baresilicon for unused cells, ink on the surface of the die that covers more than 25 percent of a bonding pad area or that bridgesany combination of unglassivated metallization or bare silicon Die mounting (low magnification). mounting material buildup that extends onto the top surface of the die or extends vertically above the top surface of the dieand interferes with to header mounting material which is not visible around at least three complete sides or 75 percent of the die criteria is not required if the devices pass an approved electrical die attach evaluation flaking of the die mounting balling of the die mounting material which does not exhibit a fillet when viewed from Die is not located or orientated in accordance with the applicable assembly drawing of the is visibly tipped or tilted (more than 10q) with respect to the die attach Internal package defects (low magnification inspection) (applicable to headers, bases, caps, and lids). As an alternative to 100percent visual inspection of lids and caps in accordance with the criteria of , the lids or caps may be subjected to a suitablecleaning process and quality verification procedure approved by the qualifying activity, provided the lids or caps are subsequently held in acontrolled environment until capping or preparation for header or post plating which is blistered, flaked, cracked, or any combination conductive particle which is attached by less than one-half of the longest bubble or a series of interconnecting bubbles in the glass surrounding the pins which are more than one-half the distancebetween the pin and body or posts which are severely glass, die, or other material greater than mil in its major dimension which adheres to the flange or side of the headerand would impair stain, varnish, or header discoloration which appears to extend under a die bond or wire isolated stud packages:(1)Any defect or abnormality causing the designed isolating paths between the metal island to be reduced to less than 50percent of the design separation.(2)A crack or chip-out in the Presence of extraneous matter. Extraneous matter (foreign particles) shall include, but not be limited foreign particle, loose or attached, greater than .003 inch ( mm) or of any lesser size which is sufficient to bridgenonconnected conducting elements of the wire tail extending beyond its normal end by more than two diameters at the semiconductor die pad or by more than fourwire diameters at the package post (see figure 2072-6). burr on a post (header lead) greater than .003 inch ( mm) in its major dimension or of such configuration that it maybreak semiconductor die bonding material buildup. A semiconductor die shall be mounted and bonded so that it is nottilted more than 10q from mounting surface. The bonding agent that accumulates around the perimeter of the semiconductordie and touches the side of the semiconductor die shall not accumulate to a thickness greater than that of the semiconductordie (see figures 2072-7 and 2072-8). Where the bonding agent is built up but is not touching the semiconductor die, the buildup shall not be greater than twice the thickness of the semiconductor die. There shall be no excess semiconductor diebonding material in contact with the active surface of the semiconductor die or any lead or post, or separated from the mainbonding material area (see figure 2072-9). on the header or posts or anywhere inside the ball bonds anywhere inside case, except for attached bond residue when rebonding is Glassivation and silicon nitride defects (high magnification). No device shall be acceptable that exhibits any of the crazing that prohibits the detection of visual criteria contained glassivation which has delaminated. (Lifting or peeling of the glassivation may be excluded from the criteria above, whenit does not extend more than mil distance from the designed periphery of the glassivation, provided that the only exposureof metal is adjacent to bond pads or of metallization leading from those pads.) by design, two or more adjacent active metallization paths which are not covered by areas at the edge of bonding pad which expose which covers more than 25 percent of the design bonding pad Post organic protective coating visual inspection. If devices are to be coated with an organic protective coating the devices shallbe visually examined in accordance with the criteria specified in prior to application of the coating. After the application and cure ofthe organic protective coating the devices shall be visually examined under a minimum of 10X magnification. Devices which exhibit any ofthe following defects shall be by design, any unglassivated or unpassivated areas or insulating substrate which has incomplete bubbles, cracks or voids in the organic protective bubble or a chain of bubbles which covers two adjacent metallized protective coating which has flaked or protective coating which is particles which are embedded in the coating and are large enough to bridge the narrowest unglassivated activemetal spacing (silicon chips shall be included as conductive particles). web of varnish (organic protective coating) that connects the wire with the Summary. The following conditions shall be specified in the applicable detail conditions, exceptions, or additions to the test applicable, any conflicts with approved circuit design topology or applicable, gauges, drawings, and photographs that are to be used as standards for operator applicable, specific 2072-1. Metallization scratches and voids (expanded contact).METHOD 2072-2. Passivation and diffusion Die with guard Die without guard 2072-3. Cracks and Tailless or crescent. NOTES: 1. d W d D (width). 2. D d L d D (length).B. ThermocompressionNOTES: NOTES: 1. D d W d D (width). 1. D d W d D (width). 2. D d L d D (length). 2. D d L d D (length).FIGURE 2072-4. Bond 2072-5. Lift/torn 2072-6. Acceptable and unacceptable voids and excessive 2072-7. Acceptable and unacceptable bonding material A NOTE: Die and wire are not necessarily 2072-8. Extraneous bonding material 2072-9. Acceptable and unacceptable excess 2073VISUAL INSPECTION FOR DIE (SEMICONDUCTOR DIODE)1. Purpose. The purpose of this test is to check the quality and workmanship of semiconductor die for compliance with therequirements of the individual specification. All tests shall be performed to detect and eliminate those die with defects that could lead todevice failures. This test will normally be used prior to installation on a 100 percent inspection basis. The test may also be employed ona sampling basis prior to encapsulation to determine the effectiveness of the manufacturer's quality control and handling Definitions. The following definitions shall area: Any area where electrical contact may be made on the "N" or "P" regions of the material (attached): Any conductive or nonconductive material that cannot be removed by a nominal gas glow(approximately 20 psi (138 kPa)). Conductive foreign material is defined as any substance that appears opaque under thoseconditions of lighting and magnification used in routine visual : The boundary between "P" and "N" type semiconductor : Silicon oxide, silicon nitride, or other insulating material that is grown or deposited directly over the "P-N" apparatus for this test shall include optical equipment and any visual standards ( , gauges, drawings, photographs)necessary to perform an effective examination and enable the operator to make objective decisions on the acceptability of thedie being examined. Adequate fixturing shall be provided for handling die without damage during otherwise specified, magnification at 20X and 30X minimum shall be performed with a monocular, binocular, or stereomicroscope. The inspection shall be performed under suitable Procedure. The die shall be examined in a suitable sequence of operations and at the specified magnifications to determinecompliance with the requirements of the individual specification and the criteria of the specified test conditions. The sequence ofexaminations required may be varied at the discretion of the Die inspections. These inspections shall apply to alloy, diffused mesa, epitaxial mesa, planar, and epitaxial planar constructiontechniques. Unless otherwise specified, inspections shall be made on a random selection of at least one side of each die beinginspected. If a lot fails, 100 percent inspection of the total lot shall be Chip-outs, cracks, and scribe line Mesa die (see figure 2073-1). Chip-outs, cracks, and scribe lines shall be a minimum of 1 mil from the junction for peakinverse voltages of less than 300 volts, and mils from the junction for voltages greater than 300 Passivated planar die (see figure 2073-2). No chip-outs, cracks, or scribe lines shall touch or extend through the inner edgesof the guard Passivation defects (see figures 2073-1 through 2073-4).METHOD 20731 of Mesa construction. There shall be no pits or voids within 1 mil from the junction. Cracks shall not extend within 1 mil of Planar construction with diffused guard ring. Devices shall be rejected for cracks in the passivation material that touch orextend through the inner edge of the guard ring, five or more bubbles, pits, or voids greater than 1 mil in diameter within the area boundedby the inner edge of the guard ring, or complete absence of passivation on the Planar construction without diffused guard ring. Device shall be rejected for total absence of passivation; or chips, cracks, orscribe lines which contact or extend into the metallized region or any pits or voids within 1 mil of the Topside contact defects (see figures 2073-1 and 2073-2). Planar construction with diffused guard ring. Devices shall be rejected if >25 percent of the design contact area is contact that extends beyond the guard rings shall be cause for Mesa die. A device shall be rejected if any contact extends over the junction or if more than 25 percent of the contact area Die size defects. Any die having 75 percent or less of its original area, 25 percent or more of the area of the adjacent die, or anyportion of the adjacent die on which the guard ring or topside contact metallization is visible even if less than 25 percent of adjacent die,shall be cause for Plating defects. A die shall be rejected if 25 percent or more of the area plating is peeled or missing from either top or back Foreign material defects. Any attached foreign matter on the surface of the die greater than 1 mil in any dimension shall because for Summary. The following conditions shall be specified in the detail inspection sampling plan (see ). magnification, where applicable (see 3.). , drawings, and photographs that are to be used as standards for operator comparison, where applicable (see 3.).METHOD 20732MIL-STD-750DPASSIVATED MESA NOTE: For peak inverse voltages of 300 V or more, the rejection criteria shall be 2 mils from the 2073-1. Passivated 20733MIL-STD-750DPASSIVATED PLANAR WITH DIFFUSED GUARD RINGFIGURE 2073-2. Passivated planar with diffused guard 20734MIL-STD-750D NOTE: For peak inverse voltages of 300 V or more, the rejection criteria shall be 2 mils from the 2073-3. Oxide passivated device with scribe moat. NOTE: For peak inverse voltages of 300 V or more, the rejection criteria shall be 2 mils from the 2073-4. Oxide passivated device without scribe 20735/6MIL-STD-750DMETHOD VISUAL INSPECTION (DISCRETE SEMICONDUCTOR DIODES)1. Purpose. The purpose of this test is to check the materials, design, construction, and workmanship of discrete semiconductordiodes and other two-terminal semiconductor devices described herein. All tests shall be performed to detect and eliminate those deviceswith defects that could lead to device failures. Opaque glass type constructions shall be examined before encapsulation. (Afterencapsulation, see MIL-STD-750, method 2068). Metal can devices shall be examined before capping. (After capping or sealing, seeMIL-STD-750, method 2071). Clear glass construction shall be examined after apparatus for these tests shall include optical equipment and any visual standards ( , gauges, drawings, photographs)necessary to perform an effective examination and enable the operator to make objective decisions on the acceptability of thedevice being examined. Any necessary fixturing for handling devices during examination to promote efficient operation withoutdamaging the units shall be otherwise specified, a monocular, binocular, or stereo microscope capable of magnification from 20X minimum to 30Xmaximum shall be used. The inspection shall be performed under suitable Procedure. The devices shall be examined at the specified magnifications to determine compliance with the requirements of theapplicable sections of this test method based on device construction. Examinations for transparent body devices may be performedanytime prior to body coating or painting. Axial lead devices shall be viewed at approximate right angles to their major axis while beingrotated through 360q. For the time interval, if any, between visual inspection and package sealing, devices shall be stored, handled, andprocessed in a manner to avoid contamination and to preserve the integrity of the devices as Small signal, computer, regulator, low power rectifiers, and microwave Axial lead, transparent body, pressure contact design. The following examinations shall be made after encapsulation (C and Sbend whisker). Glass cracks and chips (see figure 2074-1). No cracks shall be allowed in the vicinity of the cavity. Any crack originating ateither end of the package or crack that extends into the body of the glass toward the cavity more than 25 percent of the glass-to-glass orglass-to-metal seal length shall be cause for rejection. Any glass chip deep enough to expose the plug or lead surface and extendinglongitudinally into the glass-to-metal seal toward the cavity to reduce the effective seal length to less than one external lead diameter shallbe cause for Incomplete seal. All devices shall be inspected for glass-to-metal seal or glass-to-glass seal. Both seals shall be a minimum ofone external lead diameter over the entire sealed portion (sealed interface). Bubbles in seal. All devices shall be inspected for bubbles in the glass-to-metal or glass-to-glass seal. A series of bubblesthat reduce the effective seal length to less than one external lead diameter shall be cause for rejection. Bubbles in the glass, but noteffecting the glass-to-glass or glass-to-metal seal area, are not cause for Glass package deformities (see figure 2074-2). Any glass envelope deformity equal to or greater than 75 percent of theexternal lead diameter shall be cause for Extraneous matter. A device shall be rejected if there are unattached solder balls, semiconductor material, chips, flakedplating, or opaque material that is larger than the smallest distance between exposed active of 21MIL-STD-750DFIGURE 2074-1. Glass cracks and 2074-2. Package Solder protrusions (see figure 2074-3). All devices shall be inspected for solder protrusions. Any device with a protrusion thatextends more than twice the smallest protrusion width shall be 2074-3. Solder Pressure contact defects. The following misalignments or deformations shall be cause for embedded within glass body wall (see figure 2074-4).FIGURE 2074-4. Embedded contact between base of S or C spring and top surface of die caused by insufficient loading (see figure 2074-5).FIGURE 2074-5. Toe contact on top surface of die (see figure 2074-6).FIGURE 2074-6. Toe contact on top surface of contact between base of S or C spring and top surface of die (see figure 2074-7).FIGURE 2074-7. Heel contact between base of S or C spring and top surface of die except by design (deformed or twisted whisker) (see figure2074-8).FIGURE 2074-8. Point compressed height (see figures 2074-9 and 2074-10). Either half of an S or C bend that is compressed so that anydimension is reduced to less that 50 percent of its design shall be 2074-9. "S" whisker compressed 2074-10. "C" bend compressed Whisker weld to post. Any device that exhibits weld splash or splatter (teardrop or balled) between whisker and post shall berejected when it exceeds 25 percent of nominal lead diameter. The profile of the whisker weld to post shall not allow light penetration bymore than 50 percent of lead diameter when using back lighting Die to post or die to die contact area. Solder shall not be rough in appearance and shall be fused to a minimum of one-half theavailable bonding perimeter. Any solder overflow that touches the opposite surface of the die or dice shall be cause for Die alignment (see figure 2074-11). A device shall be rejected if the die surface is not within 15q of being normal to thecenterline of the mounting 2074-11. Die Lead alignment defects, (applicable to that portion of each lead within the glass envelope). A device lead which is eithermisaligned or bent so that it makes an angle with the principle device axis greater than 10q shall be Multiple chip attachment defects. A multiple chip stack that tilts more than 10q from the principle axis of the device shall because for Axial lead, metal body, solder contact Examinations before defects (see figures 2074-12 and 2074-13). Any device with a solder protrusion that extends more than twice thesmallest protrusion width shall be rejected. Solder shall be smoothly formed from one element to another and shall be fusedto a minimum of 50 percent of the perimeter between adjacent 2074-12. Solder protrusion. FIGURE 2074-13. Solder (see figure 2074-14). Any device whose element has its geometric center displaced more than 33 percent of itswidth from the die or die stack centerline shall be (see figure 2074-15). Any element of a device that is tilted more than 10q from the mounting plane shall be cause 2074-14. Element alignment. FIGURE 2074-15. Element chipouts (see figure 2074-16). Any device die that exhibits chipouts extending more than 25 percent of the die width or towithin 2 mils of the junction area shall be cause for cracks (see figure 2074-17). Any die exhibiting cracks that reduce the total die area (or cracks extending into or acrossthe junction area) to less than 75 percent of its original area shall be cause for 2074-16. Die chipout. FIGURE 2074-17. Die matter. See Axial lead transparent body straight through lead to die contact (see figure 2074-18). All inspections for glass cracks, seals,bubbles, and deformities shall be as specified in through The following additional criteria shall be specified for thestraight through construction after encapsulation but before body coating or 2074-18. Internal Die to post solder voids (see figure 2074-19). A device shall be rejected if solder flow is less than 50 percent of the perimeter of theminimum available contact area of the 2074-19. Solder overflow (see figure 2074-20). A device shall be rejected if any solder flow touches the opposite surface of the 2074-20. Solder Lead to die solder connection (see figure 2074-21). A device shall be rejected if more than 50 percent of the perimeter of theavailable contact area of the lead is void of 2074-21. Solder overflow (see figure 2074-22). A device shall be rejected if solder flow extends beyond 50 percent of the distance fromthe metal to the outer edge of the 2074-22. Solder protrusion, slivers, and spikes (see figure 2074-23). A device shall be rejected if solder slivers and spikes are notsecurely attached to the main body. A securely attached sliver of spike is one having a cross sectional area greater at the areaof attachment than anywhere else on the solder protrusion and having no necked down areas. Solder protrusions, slivers, andspikes whose length exceeds twice the smallest width of attachment shall be 2074-23. Solder slivers and balls. A device shall be rejected if there are any insecurely attached solder balls. An insecurely attached solder ball isone whose major cross sectional area is more than twice the cross sectional area of the Die to die solder connection (see figure 2074-24). A device shall be rejected if more than 50 percent of the perimeter of theavailable contact area of the die is void of 2074-24. Die to die solder Axial lead or MELF (where applicable), double plug, transparent Glass cracks (see figure 2074-25). No cracks shall be allowed in the vicinity of the cavity or die. Any spiral or meniscus crackoriginating at either end of the package or glass that extends into the body of the glass toward the die more than 25 percent of thedesigned seal length shall be cause for rejection. Any chip deep enough to expose the plug surface and extending longitudinallyinto the glass toward the die more than 25 percent of the designed seal length shall be cause for 2074-25. Glass High seal (see figure 2074-26). Any device which displays a glass case off center condition reducing the seal band of eitherplug by more than 25 percent of its designed length shall be cause for 2074-26. High Low seal (see figure 2074-27). Any anomaly such as bubbles, plug blisters, separations, leaching, or undersealing that affectsthe combined seal length of either plug by allowing a sealing band less than 50 percent of the designed seal length on any package typeshall be cause for 2074-27. Low Plug alignment (see figures 2074-28 and 2074-29). All devices shall be inspected for proper plug alignment. A plugdisplacement distance more than 25 percent of the diameter of the plug shall be cause for rejection. The plug shall not tilt to the degreethat it touches the chip or is misaligned from the other plug axis more than 2074-28. Plug 2074-29. Plug Extraneous matter. A device shall be rejected if there are unattached solder balls, semiconductor material, chips, flakedplating, or opaque material that is larger than the smallest distance between exposed active Lead connections (see figure 2074-30). Lead to plug connections shall be inspected for incomplete welds. Any partial weldsless than 75 percent of total weld area shall be cause for 2074-30. Incomplete Axial lead, transparent body, point contact. All inspections for glass cracks, seals, bubbles, and deformities shall be as specifiedin through The following additional criteria shall be specified for the point contact construction after encapsulation butbefore body coating or Pressure contact defects. The following misalignments or deformities shall be cause for touches glass body wall (see figure 2074-31).FIGURE 2074-31. Whisker touches glass body wall (reject). loops touch one another (see figure 2074-32).FIGURE 2074-32. Whisker loops touch one another (reject).METHOD angle over 10q from normal (see figure 2074-33).FIGURE 2074-33. Whisker angle over 10q from normal (reject). Whisker weld to post. Any device that exhibits weld splash or splatter (tear dropped or balled) between whisker and post shallbe rejected when it exceeds 25 percent of nominal lead diameter. The profile of whisker weld to the post shall not allow light penetrationby more than 50 percent of lead diameter when using back lighting Solder voids. A device shall be rejected if solder flow is less than 50 percent of the perimeter of the minimum available contactarea of the Die to post contact area. Solder shall be smoothly formed from one element to another and shall be fused to a minimum ofone-half the available bonding area. Any solder overflow that touches the opposite surface of the die shall be cause for Die alignment. A device shall be rejected if the die surface is not within 15q of being normal to the centerline of the Lead alignment defects (applicable to that portion of each lead within the glass envelope). A device whose lead is eithermisaligned or bent so that is makes an angle with the principle device axis greater than 10q shall be Die touches glass package (see figure 2074-34). A device shall be rejected if the die touches the glass 2074-34. Die touches glass package (reject).METHOD Power rectifiers and Axial lead double plug opaque Die mounting and alignment. After bonding die to the heat sink, plugs, or leads, the following shall be inspected for geometry. A die shall be rejected if it is chipped or broken to the extent that 75 percent or less of the original alignment of plugs and die. Plugs shall be aligned axially within one-eighth of the diameter of either die. A device shall be rejected if the die is tilted so that the die surface is greater than 5q from being perpendicular tothe mounting post Die cracks. Any die exhibiting cracks that reduce the total die area (or cracks extending into or across the junction area) toless than 75 percent of its original area shall be cause for Inadequate brazing. A device shall be rejected if less than 90 percent of the visible metallized surface (perimeter) is brazed tothe heat sink or Flaking or loose material. No unattached solder, braze, or other bonding material shall extend from the plugs. Any blistering orpeeling of plug surface shall be cause for Extraneous matter. A device shall be rejected if there is any extraneous, particulate matter between the terminal plugs or onthe plug surface. No foreign stains shall be permitted on plug Axial lead, double plug, transparent body. The inspections in through may be performed on a sealed device if allinspection criteria are clearly visible and detectable. After bonding the die to the heat sink, plugs, or leads, the following shall beinspected for Axial alignment of plugs and die. Plugs shall be aligned within one-eighth of the diameter of either Tilted die. A device shall be rejected if the die is tilted so that the die surface is greater than 5q from being perpendicular to themounting post Inadequate brazing. A device shall be rejected if less than 90 percent of the visible metallized surface (perimeter) is brazed tothe heat sink or Flaking or loose material. No unattached solder, braze, or other bonding material shall extend from the plugs. Any blistering orpeeling of plug surface (cavity type) shall be cause for rejection. Any blistering or peeling of plug surface (non-cavity type) which reducesdesigned seal length to less than 25 percent shall be cause for Extraneous matter. A device shall be rejected if there are unattached solder balls, semiconductor material, chips, flakedplating, or opaque material that is larger than the smallest distance between exposed active Cracks in glass. No cracks shall be allowed in the vicinity of the cavity. Any crack originating at either end of the package orcrack that extends into the body of the glass toward the cavity more than 25 percent of the glass-to-glass or glass-to-metal seal lengthshall be cause for rejection. Any glass chip deep enough to expose the plug, or lead surface and extending longitudinally into the glass-to-metal seal toward the cavity to reduce the effective seal length to less than one external lead diameter shall be cause for Glass bubbles. All devices shall be inspected for bubbles in the glass-to-metal or glass-to-glass seal. A series of bubbles thatreduce the effective seal length to less than one external lead diameter shall be cause for Encapsulant position. A device shall be rejected if the encapsulant covers less than 80 percent of the design plug Metal body devices. The following inspections shall be made prior to Die and lead assembly (see figures 2074-35 and 2074-36). The die and lead assembly shall be located on the base pedestalso that there is complete contact over the design contact area. The lead shall be free of nicks and scrapes that reduce the lead diameterby more than 5 percent. The die and lead assembly shall not be tilted more than 5q with respect to the 2074-35. Offset 2074-36. Tilted Extraneous slivers and spikes. A device shall be rejected if solder slivers and spikes are not securely attached to the parent bodyof the solder. A securely attached sliver or spike is one having a cross sectional area greater at the area of attachment thananywhere else on the solder protrusion and having no necked-down matter. A device shall be rejected if there are unattached solder balls, semiconductor materials, chips, flaked plating,or opaque material that is larger than the smallest distance between exposed active die attachments. A device shall be rejected if the attached portion of an adjacent die exceeds 25 percent of the Assembly elements. A device shall be rejected if any element of the assembly is tilted in excess of 10q from the normal elements. A device shall be rejected if any element of the assembly is misaligned or displaced in excess of 33percent of its width from the die or die stack centerline, bridges two active regions, or extends beyond the isolation region ofthe Metal body diamond base regulators (see figure 2074-37).FIGURE 2074-37. Diamond base Die to pedestal and die to clip solder voids. A device shall be rejected if solder flow is less than 50 percent of the perimeter of the minimum availablecontact overflow. A device shall be rejected if any solder flow bridges from the top to bottom surface of the die or reduces thenormal separation of two active regions by 50 percent or Clip to post and feed through to heat sink solder voids. A device shall be rejected if the wetting action of the solder to each member of the connection is not overflow. A device shall be rejected if any solder flow extends on to any portion of the weld flange of the heat requirements for materials, design, construction, and requirements, if other than 2075DECAP INTERNAL VISUAL DESIGN VERIFICATION1. Purpose. The purpose of this examination is to verify that design and construction are the same as those documented in thequalified design report and for which qualification approval has been granted. This test is destructive and would normally be employed ona sampling basis during qualification or quality conformance inspection of a specific device Apparatus. Equipment used in this examination shall be capable of demonstrating conformance to the requirements of theapplicable acquisition document and shall include optical equipment with sufficient magnification to verify all structural features of Procedure. Devices shall be selected at random from the inspection lot and examined using sufficient magnification to verify thatdesign and construction are in accordance with the requirements of the applicable design documentation or other specific requirements(see 4.). Specimens of constructions which do not contain an internal cavity ( , sealed or embedded devices) or those which wouldexperience destruction of internal features of interest as a result of opening, may be obtained from manufacturing prior to of constructions with an internal cavity shall be selected from devices which have completed all manufacturing operations andthey shall be delidded or opened taking care to minimize damage to the areas to be inspected. When specified by the applicable detailspecification, specimens of constructions with an internal cavity may be obtained from manufacturing prior to Photographs of die topography and intraconnection pattern. When specified, a color photograph or transparency shall be madeshowing the topography of elements formed on the die or substrate and the metallization pattern. This photograph shall be at a minimummagnification of 80X except that if this results in a photograph larger than x inches ( x mm), the magnification maybe reduced to accommodate the x inches ( x mm) Failure criteria. Devices which fail to meet the detailed requirements for design and construction shall constitute a Summary. The following conditions shall be specified in the detail applicable requirements for design and for obtaining internal cavity devices prior to encapsulation (see 3.). for photographic record, if applicable (see ), and disposition of 20751/2MIL-STD-750DMETHOD Purpose. The purpose of this examination is to nondestructively detect defects within the sealed case, especially those resultingfrom sealing of the lid to the case, and internal defects such as foreign objects, improper interconnecting wires, and voids in the dieattach material or in the glass when glass seals are used. This test establishes methods, criteria, and standards for radiographicexamination of discrete :For certain case types, the electron shielding effects of device construction materials (packages or internal) may effectivelyprevent radiographic identification of certain types of defects from some or all possible viewing angles. This factor should beconsidered in relation to the design of each when application of this test method is Apparatus. The apparatus and materials for this test shall equipment with a sufficient voltage range to penetrate the device. The focal distance shall be adequate tomaintain a sharply defined image of a object with a major dimension of .001 inch ( mm). film: (Eastman type R or equivalent). viewer capable of .001 inch ( mm) resolution in any major fixtures capable of holding devices in the required positions without interfering with the accuracy or ease of quality standards capable of verifying the ability to detect all specified defects for particular package types .062 inch ( mm) minimum lead topped table shall be used to prevent back scatter of Procedure. The x-ray exposure factors, voltage, milliampere setting and time settings shall be selected or adjusted as necessary toobtain satisfactory exposures and achieve maximum image details within the sensitivity requirements for the device or defect features theradiographic test is directed toward. Unless otherwise specified, the x-ray voltage shall be the lowest consistent with these requirementsand shall not exceed 150 kV. Although higher voltages may be necessary to penetrate certain packages, these levels may be damagingto some device Mounting and views. The devices shall be mounted in the holding fixture so that the devices are not damaged or contaminated andare in the proper plane as specified. The devices may be mounted in any type of fixture and masking with lead diaphragms or barium claymay be employed to isolate multiple specimens provided the fixtures or masking materials do not block the path of the x-rays to the film orany portion of the otherwise specified, flat packages and single ended cylindrical devices shall have one view taken with the x-rayspenetrating in the Y direction as defined in figures 1 and 2 of the general requirements herein. When more than one view isrequired, the second and third views, as applicable, shall be taken with the x-rays penetrating in the X and Z otherwise specified, stud-mounted and cylindrical axial lead devices shall have one view taken with the x-rayspenetrating in the X direction as defined in figures 1 and 2 of the general requirements herein. When more than one view isrequired, the second and third views, as applicable, shall be taken with the x-rays penetrating in the Z direction and at 45Ebetween the X and Z JANS devices shall have two views taken with x-rays penetrating in the X and Y directions, stud-mounted and axial leaddevice views shall be taken with x-rays penetrating in the X and Z of Radiographic quality standard. The radiographic quality standard shall consist of a suitable standard penetrameter such asradiographic quality standard ASTM type B - Image quality indicator for semiconductor radiography or equivalent device. Each radiographshall have two image quality standards exposed with each view located (and properly identified) in opposite corners of the film. Theradiographic density of penetrameters chosen shall bracket the density of the devices beings Film and marking. The radiograph film shall be in a film holder backed with a minimum of .062 inch ( mm) lead or the holdershall be placed on the lead topped table (see ). The film shall be identified using techniques that legibly print the following information,photographically on the manufacturer's name or code identification type or Part or Identifying Number (PIN). lot number, date code, or inspection lot film view number and serial or cross reference numbers, when applicable (see ). laboratory identification, if other than device axis view (X, Y, or Z). Nonfilm techniques, when specified. The use of nonfilm techniques is permitted under the following records are not equipment is capable of producing results of equal quality when compared with film requirements of this method are complied with except those pertaining to the actual Serialized devices. When device serialization is required, each device shall be readily identified by a serial number. The devicesshall be radiographed in consecutive, increasing serial order. When a device is missing, the blank space shall contain either the serialnumber or other x-ray opaque objects to readily identify and correlate the x-ray data. When more than one consecutive device is missingwithin serialized devices, the serial number of the last device before the skip and the first device after the skip may, at the manufacturersoption, be used in place of the multiple opaque Special device marking. When specified (see ), the devices that have been x-rayed and found acceptable shall be identifiedwith a blue dot on the external case. The blue dot shall be approximately .062 inch ( mm) in diameter. The color selected fromFED-STD-595 shall be any shade between 15102-15123 or 25102-25109. The dot shall be placed so that it is readily visible but shall notobliterate other device Tests. The x-ray exposure factor shall be selected to achieve resolution of .001 inch ( mm) major dimension, less than 10percent distortion and an "H" and "D" film density between 1 and in the area of interest of the device image. Radiographs shall bemade for each view required (see 4.). Processing. The radiographic film manufacturer's recommended procedure shall be used to develop the exposed film, and filmshall be processed so that it is free of processing defects such as fingerprints, scratches, fogging, chemical spots, Operating personnel. Personnel who will perform radiographic inspection shall have training in radiographic procedures andtechniques so that defects revealed by this method can be validly interpreted and compared with applicable standards. The followingminimum vision requirements shall apply for visual acuity of personnel inspecting film as well as personnel authorized to conductradiographic vision shall equal at least 20/30 in both eyes, corrected or vision shall be such that the operator can read Jaegger type No. 2 at a distance of 16 inches ( mm), corrected tests shall be performed by an oculist, optometrist, or other professionally recognized personnel at least once a Interpretation of radiographs. Utilizing the equipment specified herein, radiographs shall be inspected to determine if each deviceconforms to this standard or if it is defective and shall be rejected. Interpretation of the radiograph shall be made under low light levelconditions without glare on the radiographic viewing surface. The radiographs shall be examined on a suitable illuminator with variableintensity or on a viewer suitable for radiographic inspection on projection type viewing equipment. The radiograph shall be viewed at amagnification between 6X and 20X. Viewing masks may be used when necessary. Any radiograph not clearly illustrating the features inthe radiographic quality standards is not acceptable and another radiograph of the devices shall be Reports and Reports of inspection. For JANS devices, or when specified for other device classes, the manufacturer shall furnish inspectionreports with each shipment of devices. The report shall describe the results of the radiographic inspection, and list the purchase ordernumber or equivalent identification, the PIN, the date code, the quantity inspected, the quantity rejected, and the date of test. For eachrejected device, the PIN, the serial number, when applicable, and the cause for rejection shall be Radiograph submission. When specified, one set of the applicable radiographs shall accompany each shipment of Radiograph and report retention. When specified, the manufacturer shall retain a set of the radiographs and a copy of theinspection report. These shall be retained for the period Examination and acceptance Device construction. Acceptable devices shall be of the specified design and construction with regard to the characteristicsdiscernible through radiographic examination. Devices that deviate significantly from the specified construction shall be Individual device defects. The individual device examination shall include, but not be limited to, inspection for foreign particles,solder or weld "splash" build up of bonding material, proper shape and placement of lead wires or whiskers, and bond of lead or whiskerto semiconductor element. Devices for which the radiograph reveals any of the following defects shall not be Unacceptable construction. In the examination of devices, the following aspects shall be considered unacceptableconstruction and devices that exhibit any of the following defects shall be contact area voids in excess of one-half of the total contact single void which traverses either the length or width of the semiconductor die and exceeds 10 percent of the total intendedcontact area.(1)Voids: When radiographing devices, certain types of mounting do not give true representations of voids. When suchdevices are inspected, the mounting shall be noted on the inspection report (see figure 2076-1).(2)Wires present, other than those connecting specific areas of the semiconductor die to the external leads.(3)Angle between semiconductor die surface and edge less than 45q.(4)Defective seal: Any device wherein the integral lid seal is not continuous or is reduced from its designed sealing widthby more than 75 :Expulsion resulting from the final sealing operation is not considered extraneous material as long as it can beestablished that it is continuous, uniform, and attached to the parent material and does not exhibit a ball,splash, or tear-drop configuration.(5)Inadequate clearance: Acceptable devices shall have adequate internal clearance to assure that the elements cannotcontact one another or the case. No crossover of wires connected to different electrical elements shall be upon the case type, devices shall be rejected for the following conditions:(a)Flat pack and dual-in-line (see figure 2076-2). lead wire that appears to touch or cross another lead wire or bond (Y plane only). lead wire that deviates from a straight line from bond to external lead and appears to be within .002 inch( mm) of another bond (Y plane only). wires that do not deviate from a straight line from bond to external lead and appear to touch anotherwire or bond (Y plane only). lead wire that touches or is less than .002 inch ( mm) from the case or external lead to which it isnot attached (X and Y plane). bond that is less than .001 inch ( mm) (excluding bonds connected by a common conductor)from another bond (Y plane only). wire making a straight line run (with no arc) from die bonding pad to package post.(b)Round or "box" transistor type (see figure 2076-3). lead wire that touches or is less than .002 inch ( mm) from the case or external lead to which it isnot attached (X and Y plane). wires that sag below an imaginary plane across the top of the bond (X plane only). lead wire that appears to touch or cross another lead wire or bond (Y plane only) if bonded to differentelectrical lead wire that deviates from a straight line from bond to external lead appears to touch or to be inch ( mm) of another wire or bond (Y plane only).METHOD bond that is less than .001 inch ( mm) (excluding bonds connected by a common conductor)from another bond (Y plane only). wire making a straight line run (with no arc) from die bonding pad to package post, unless specificallydesigned in this manner ( , clips, rigid connecting leads, or heavy power leads). internal post that is bent more than 10q from the vertical (or intended design position) or is not uniformin length and construction or comes closer than one post diameter to another post in a low profile case (such as a TO-46) which comes closer to the top of the case than 20 percentof the total inside dimension between the header and the top of the case. Any device in which thesemiconductor element is vertical to the header, and comes closer than .002 inch ( mm) to theheader or to any part of the case.(c)Axial lead type (see figure 2076-4). embedded within glass body tilted more than 5q in any direction from the device lead axis or deformed to the extent that ittouches half of an S or C bend whisker that is compressed so that any dimension is reduced to less than 50percent of its design value. On diodes with whiskers metallurgically bonded to the post and to the die, thewhisker may be deformed to the extent that it touches itself if the minimum whisker clearance zone specifiedin figure 2076-4a is maintained for metal construction device with plug displacement distance more than one-fourth of the diameter ofthe plug with respect to the central axis of the element mounting tilted more than 15E from normal to the main axis of the hanging over edge of header or pedestal more than 20 percent of the die contact area by than 75 percent of the semiconductor element base area is bonded to the mounting in the welds which reduce the lead to plug connection by more than 25 percent of the total weld with package deformities such as body glass cracks, incomplete seals ( , voids, position ofglass), die chip outs, and severe misalignment of S- and C-shaped whisker connections to die or post thatexceed the limits of the applicable visual inspection Encapsulated non-cavity assemblies of discrete devices. External to the individual devices, the encapsulating material shall beexamined and rejected for the following Extraneous material. Extraneous matter of any shape with any dimension exceeding .020 inches ( mm). Also, any twoadjacent particles of such matter with total dimensions exceeding .030 inches ( mm).METHOD Summary. The following conditions shall be specified in the applicable detail of views, if other than indicated in and submission, if applicable (see ). , if other than indicated in and marking of samples to indicate they have been radiographed, if required (see ). defects and criteria for acceptance or rejection, if other than indicated in and report retention, if applicable (see ). reports when 2076-1. Acceptable and unacceptable voids and excessive 2076-2. Clearance in dual-in-line or flat pack type 2076-3. Clearance in round or box transistor type 2076-4. Clearance in cylindrical axial lead type ELECTRON MICROSCOPE (SEM) INSPECTION OF METALLIZATION1. Purpose. This method provides a means of judging the quality and acceptability of metallization on semiconductor dice. Itaddresses the specific metallization defects that are batch process oriented and which can best be identified utilizing this method. Itshould not be used as a test method for workmanship and other type defects best identified using the visual inspection criteria of method2072. The term "dice" for the purpose of this test method, includes diodes and transistors which have expanded metallization contacts ormetallization Apparatus. The apparatus for this inspection shall be a SEM having an ultimate resolution of 100 or less and a variablemagnification to at least 20,000X. The apparatus shall be such that the specimen can be tilted to a viewing angle (see figure 2077-1) of60q or greater, and can be rotated through 360q. Evidence of using competent SEM operating personnel as well as acceptabletechniques and equipment that meet the requirements of this method shall be demonstrated for the approval of the qualifying activity or,when applicable, a designated representative of the acquiring Sample selection. Proper sampling is an integral part of this test method. Statistical techniques, using random selection, are notpractical here because of the large sample size that would be required. This test method specifies means of minimizing test sample whilemaintaining confidence in test integrity by designating for examination wafers in specific locations on the wafer holder(s) in themetallization chamber, and specific dice on the wafers. These dice are in typical or worst case positions for the metallizationconfiguration. Dice selected for SEM examination shall not be immediately adjacent to the wafer edge, and they shall be free of smearingor inking, since this could obscure processing faults for which they are to be inspected. Metallization acceptance shall be based onexamination of sample dice, using either a single wafer acceptance basis or a process lot acceptance basis. A process lot is a batch ofwafers which has been received together those common processes which determine the slope and thickness of the oxide step and whichhave been metallized as a Sampling condition A, unglassivated devices. This sampling condition applies to devices which have no glassivation over themetallization. Steps 1 and 2, which follow, both apply when acceptance is on a lot acceptance basis. Only step 2 applies whenacceptance is on a single wafer acceptance Step 1: Slice selection. From each lot to be examined on a lot acceptance basis, wafers shall be selected from the designatedpositions on the wafer holder(s) in the metallizing chamber. In accordance with the definition of lot in , if there is more than oneprocess lot in a metallization chamber, each process lot shall be grouped approximately in a separate sector within the wafer holder, and aseparate set of wafers shall be selected for each process lot being examined on a lot acceptance basis. Table 2077-I and figure 2077-2specify the number and sites of wafers to be selected. Dice selection from the selected wafers shall be in accordance with the samplingplan established for a single wafer in step 2 (see ). Step 2: Dice selection. When a wafer is to be evaluated (for acceptance on a single wafer basis, or with one or more waferson a lot acceptance basis), either of the following sampling conditions may be used at the manufacturer's Sampling condition A1: Quadrants. Immediately following the dicing operation ( , scribe and break, saw, etch) and beforerelative die location on the wafer is lost, four dice shall be selected. The positions of these dice shall be near the periphery of the waferand approximately 90q apart (see figure 2077-2). Sampling condition A2: Segment. After completion of all processing steps and, prior to dicing, two segments shall beseparated from opposite sides of each wafer to be examined. These segments shall be detached along a chord approximately one-thirdof the wafer radius in from the edge of the wafer. One die from near each end of each segment ( , four dice) shall then be subjected toSEM of 26MIL-STD-750DTABLE 2077-I. Wafer sampling procedures. Metallization chamberconfigurationNumber ofprocess lotsin chamber 1/Required number of samples inaccordance with process lotSampling plan in accordancewith process lotEvaporationSputteringProjected plane view of the wafer holder is a circle. Wafer holder is stationary or "wobbulates".152Four from near the periphery of the wafer holder and 90q apart. One from the center of the holder. See figure , 4, or 52See figures 2077-2b or or 42See figure figure holder is symmetrical ( , circular, square). Deposition source(s) is above or below the wafer holder. Wafer holder rotates about its center during , 2, 3, or 422For each process lot, one from the periphery of the wafer holder, and from close proximity to the center of rotation. See figure system. One or more symmetrical wafer holders (planets) rotate about their own axes while simultaneously revolving about the center of the chamber. Deposition source(s) is above or below the wafer , 2, 3, or 4 perplanet22For each process lot, one from near the periphery of a planet, and one from near the center of the same planet. 2/ See figure there is more than one process lot in a metallization chamber, each process lot shall be grouped approximatelyin a separate sector within the wafer holder. A sector is an area of the circular wafer holder bounded by tworadii and the subtended arc; quadrants and semicircles are used as examples on figure wafers need to be selected from only one planet if all process lots contained in the chamber areincluded in that planet. Otherwise, sample wafers of the process lot(s) not included in that planet shall beselected from another planet(s).NOTE: If a wafer holder has only one circular row, or if only one row is used on a multi-rowed wafer holder, the total number of a specified sample wafers shall be taken from that Sampling condition C: Glassivated devices. This sampling condition applies to devices which have glassivation over themetallization. Steps 1 and 2, which follow, both apply when acceptance is on a lot acceptance basis. Only step 2 applies whenacceptance is on a single wafer acceptance Step 1: Wafer selection. From each lot to be examined on a lot acceptance basis, wafers shall be selected from thedesignated positions on the wafer holder in the metallizing chamber. In accordance with the definition of lot in , if there is more thanone process lot in a metallization chamber, each process lot shall be grouped approximately in a separate sector within the wafer holder,and a separate set of wafers shall be selected for each process lot being examined on a lot acceptance basis. Table 2077-I and figure2077-2 specify the number and sites of wafers to be selected. Dice selection from the selected wafers shall be in accordance with thesampling plan established for a single wafer in step 2 (see ). Step 2: Dice selection. When a wafer is to be evaluated (for acceptance on a single wafer acceptance basis, or with one ormore other wafers on a lot acceptance basis), any of the following sampling conditions may be used at the manufacturer's Sampling condition B1: Quadrants. This is the recommended condition for glassivated devices. Immediately following thedicing operation ( , scribe and break, saw, etch) and before relative die location on the wafer is lost; four dice shall be selected. Thepositions of these dice shall be near the periphery of the wafer and approximately 90q apart. The glassivation shall then be removed fromthe dice using a suitable etch. It is recommended that the etchant used have an etch rate for the glassivation which is approximately 200times that for the metallization. The dice shall be periodically examined during glass removal using a bright field metallurgical microscopeto determine when all the glassivation has been removed and to minimize the possibility of etching the Sampling condition B2: Segment, prior to glassivation. This sampling condition may be used only if the glassivationprocessing temperature is lower than +400 C. Two segments shall be separated from opposite sides of each wafer to be examinedimmediately before the glassivation coating operation; , subsequent to metallization, etching, and sintering, but before segments shall be detached along a chord approximately one-third of the wafer radius in from the edge of the wafer. One die fromnear each end of each segment ( , four dice) shall be subjected to SEM Sampling condition B3: Segment, after glassivation. Two segments shall be separated from opposite sides of each wafersubsequent to sintering and glassivation. These segments shall be detached along a chord approximately one-third of the wafer radius infrom the edge of the water. The glassivation shall then be removed from the segment using a suitable etch (see for the etchrate). The segment shall be periodically examined using a bright field metallurgical microscope to determine when all the glassivation hasbeen removed and to minimize the possibility of etching the metallization. One die from near each end of each segment ( , four dice)shall be subjected to SEM Lot control during SEM examination. After dice sample selection for SEM examination, the manufacturer may elect either of Option 1. The manufacturer may continue normal processing of the lot with the risk of later recall and rejection of product ifSEM inspection, when performed, shows defective metallization. If this option is elected, positive control and recall of processed materialshall be demonstrated by the manufacturer by having adequate traceability Option 2. Prior to any further processing, the manufacturer may store the dice or wafers in a suitable environment until SEMexamination has been completed and approval for further processing has been Specimen preparation. Specimens shall be mounted in an appropriate manner for examination. Suitable caution shall beexercised in the use of materials such as conducting paints and adhesives for specimen mounting so that important features are notobscured. Specimens may be examined without any special coating to facilitate SEM examination if the required resolution can beobtained, or they may be coated with a vapor-deposited or sputtered film of a suitable conductive material. If the specimens are coated,thickness or quality of the coatings shall be such that no artifacts are Specimen examination, general requirements. The metallization on all four edge directions shall be examined on each die for eachtype of contact window step and for each other types of oxide steps (see table 2077-II) (oxide refers to any insulating material used on thesemiconductor die, whether SiOx or SiNx). A single window (or other type of oxide step) may be viewed if metallization covers the entirewindow (or other type of oxide step) extending up to and over each edge and onto the top of the oxide at each edge. Other windows (orother types of oxide steps) on the die shall be examined to meet the requirement that all four directional edges of each type of window (orother type of oxide step) shall be examined on each die. General metallization defects, such as peeling and voids, shall be viewed toprovide for the best examination for those 2077-II. Examination procedure for sample typeArea ofexaminationExaminationMinimum - maximummagnificationPhotographicdocument ation1 Expanded contact bipolar and power FET'sOxide step 2/ (contact windows and other types of oxide steps)All4,000Xto20,000XTwo of the worst case oxide metallization 3/All1,000Xto6,000XWorst case general metalli- (an additional photograph may be required).2/Scanning examination shall include all four directional edges of oxide steps (documentation need only show the worstcase). Oxide steps include contact windows (emitters, bases, collectors, drains, sources, diffused resistors) and othertypes ( , diffusion cuts for emitters, bases, collectors; and field oxide steps). See for accept/reject for accept/reject :For multi-layered-metal interconnection systems, see and Window coverage also shall be Viewing angle. Specimens shall be viewed at an appropriate angle to accurately assess the quality of the metallization. Contactwindows are normally viewed at an angle of 45q to 60q or greater (see figure 2077-1). Viewing direction. Specimens shall be viewed in an appropriate direction to accurately assess the quality of the inspection shall include examination of metallization at the edges of contact windows and other types of oxide steps (see ) in anydirection that provides clear views of each edge and that best displays any defects at the oxide step. The viewing direction may beperpendicular to an edge, parallel with an edge, or at some oblique Magnification. The magnification ranges shall be between 4,000X and 20,000X for examination of oxide steps and between1,000X and 6,000X for general metallization defects, such as peeling and voids (refer to table 2077-II). When dice are subjected toreinspection, such reinspection shall be accomplished at any magnification within the specified Specimen examination detail Expanded contact bipolar. Examination shall be as specified herein and summarized in table Oxide steps. Inspect the metallization at all types of oxide steps (see table 2077-II) and document in accordance with General metallization. Inspect all general metallization on each die for defects such as peeling and voids. Document inaccordance with Power FET's. Examination shall be specified herein and summarized in table Oxide steps. Inspect the metallization at all types of oxide steps (see table 2077-II) and document in accordance with ForRF or power transistors with interdigitated or mesh structures, each base-emitter stripe pair within each pattern shall be inspected as aminimum. Particular attention shall be directed to lateral etching defects and undercut at base and emitter oxide steps. Documentationshall be as specified in General metallization. Inspect all general metallization on each die for defects such as peeling and voids. Document inaccordance with Multi-layered metal interconnection systems. Multi-layered metal is defined as two or more layers of metal or any other materialused for interconnections. Each layer of metal shall be examined. The principal current-carrying layer shall be examined with the SEM;the other layers (for example, barrier or adhesion) may be examined using either the SEM or an optical microscope, at the manufacturer'soption. Accept/reject criteria for multi-layered metal systems are given in The glassivation (if any) and each successive layer ofmetal shall be stripped by selective etching with suitable reagents, layer-by-layer, to permit the examination of each layer. If it isimpractical to remove the metal on a single die layer-by-layer, one or more dice immediately adjacent to the original die shall be etch sothat all layers shall be exposed and examined. Specimen examination shall be in accordance with Acceptance Single slice acceptance basis. The metallization of a wafer shall be judged acceptable only if all sample dice from that wafer Lot acceptable basis. An entire lot shall be judged acceptable only when all sample dice from all sample wafers are the manufacturer's option, if a lot is rejected in accordance with this paragraph, each wafer from that lot may be individually shall then be in accordance with Accept/reject criteria. Rejection of dice shall be based upon batch process oriented defects. Rejection shall not be based uponworkmanship and other type defects such as scratches, smeared metallization, tooling marks. In the event that the presence of suchdefects obscures the detailed features being examined, an additional die shall be examined which is immediately adjacent to the die withthe obscured metallization. Illustrations of typical defects are shown on figure 2077-4 through figure Oxide steps. The metallization on all four directional edges of every type of oxide steps (contact window or other type of oxidestep) shall be examined (see ). The metallization shall be unacceptable if thinning and one or more defects such as voids,separations, notches, cracks, depressions, or tunnels reduce the cross-sectional area of the metal at the directional edge to less than 50percent of metal cross-sectional area on either side of the directional edge. When less than 50 percent, for the metallization to beacceptable, all four directional edges shall be covered with metallization (see ) and shall be acceptable except in the cases describedin and Oxide steps without metallization. In the event that a directional edge profile of a particular type of oxide step cannot be foundwhich is covered with metallization (see ) and therefore, a judgment of the quality of the metallization at that directional edge profilecannot be made, this shall not be cause for rejection is established that the edge profile from which metal is absent does not occur in a current-carrying direction, suchdetermination being made either by scanning all oxide steps of this type on the balance of the die, or by examination of atopographical map supplied by the manufacturer which shows the metal interconnect pattern, and; sample wafers are examined, these duplicates being located adjacent to the original sample wafers, in thewafer holder, and being rotated so as to be oriented approximately 180q with respect to the original sample wafersduring metallization. If the conditions of both a. and b. are met, a lot acceptance basis may be used. If only condition ais met, a single wafer acceptance basis must be Oxide steps with less than 50 percent metallization. If less than the specified percent of the metallization is present at aparticular directional edge profile (see figure 2077-3), wafer lot rejection shall not be invoked is established that the edge profile from which metal is absent does not occur in a current-carrying direction, suchdetermination being made either by scanning all oxide steps of this type on the balance of the die, or by examination of atopographical map supplied by the manufacturer which shows the metal interconnect pattern; is on a wafer basis only, and; device is a power FET, no less than 30 percent of the metallization is present and the maximum calculated currentdensity does not exceed the value which corresponds to the applicable conductor material in accordance with 2077-III. Conductor material. |||| Conductor material| Maximum allowable continuous||| current density (RMS for|| | pulse applications) ||||| Aluminum ( percent pure or doped)| 2 x 105 amps/cm2|| without glassivation|||||| Aluminum ( percent pure or doped)| 5 x 105 amps/cm2|| with glassivation|||||| Gold| 6 x 105 amps/cm2||||| All other (unless otherwise specified)| 2 x 105 amps/cm2|| | | General metallization. General metallization is defined for the purpose of this test method as the metallization at all locationsexcept at oxide steps, and shall include metallization (stripes) in the actual contact window regions. Any metallization pulling or lifting(lack of adhesion) shall be unacceptable. Any defects, such as voids which reduce the cross-sectional area of the metallization stripe bymore than 50 percent shall be Multi-layered metal interconnection systems. These systems may be more susceptible to undercutting than single-layered metalsystems and shall, therefore, be examined carefully for this type of defect, in addition to the other types of defects. Refer to forspecimen examination requirements and definition of multi-layered metal Oxide steps. Criteria of shall apply to both the principal conducting metal and the barrier layer. If by design, a barrierlayer is not intended to cover the oxide steps, shall not apply to the barrier Barrier or adhesion layer as a nonconductor. When a barrier or adhesion layer is designed to conduct less than ten percentof the total current, this layer must be considered as only a barrier or adhesion layer. Consequently, this barrier or adhesion barrier layershall not be used in current density calculations and shall not be required to satisfy the step coverage requirements. The barrier oradhesion layer shall be required to cover only these regions where the barrier function is designed with the manufacturer providingsuitable verification of this function. The thickness of the barrier or adhesion layer shall not be permitted to be added to the thickness ofthe principal conducting layer when estimating the percentage metallization step coverage. Therefore, the principal conducting layer shallsatisfy the percentage step coverage by General metallization. Criteria of shall apply here only for the principal conducting metal layer. Other metal layers(nonprincipal conducting layers such as barrier or adhesion layers) may be examined with the SEM, or with an optical microscope, thechoice of equipment being at the manufacturer's option. Two specific cases of general metallization are considered. In the examinationof other metal layers for the specific case of interconnection stripes ( , exclusive of contact window area), a defect consuming 100percent of the cross-sectional area of the strip shall be acceptable provided the length of that defect is not greater than the width of themetallization strip (see figure 2077-22). For the specific case of contact window area metallization, at least 70 percent of the contactwindow area must be covered by the principal metal layer and any underlying metal layer(s); for the metal layer(s) above the principalconducting layer in the contact window area, a defect consuming 100 percent of the cross-sectional area of the metallization strip shall beacceptable provided the length of that defect is not greater than the width of the stripe. In the examination of the specific case of contactwindow area metallization for multi-metal systems, at least one of each type of contact window present shall be Specimen documentation requirements. After examination of dice from each wafer, a minimum of three photographs per lot shallbe taken and retained. Two photographs shall be of worst case oxide steps and the third photograph of worst case general any photograph shows another apparent defect within the field of view, another photograph shall be taken to certify the extent of thatapparent defect (see table 2077-II). Required information. The following information shall be traceable to each 's lot identification operator/inspector's of SEM identification (type or PIN). of photographic beam accelerating Control of samples. SEM samples may not be shipped in any manner as functional Summary. The following conditions shall be specified in the applicable acquisition slice acceptance basis when required by the acquiring for photographic documentation (number and kind) if other than as specified in 2077-1. Viewing 2077-2. Wafer sampling procedures (refer to table 2077-II).METHOD 2077-2. Wafer sampling procedures (refer to table 2077-II) - 2077-3. Concept of reduction of cross-sectional area of metallization as accept/reject criteria (any combination of defects and thinning over a step which reduces the cross-sectional area of the metal to less than 50 percent of metal cross-sectional area as deposited on the flat surface, is cause for rejection).METHOD 2077-4. (6,000X) Void near oxide step (accept).FIGURE 2077-5. (3,300X) Voids at oxide step (reject).METHOD 2077-6. (8,000X) Voids at contact (reject).NOTE: Tunnel does not reduce cross-sectional area more than 50 2077-7. (10,000X) Tunnel/cave at oxide step (accept).METHOD 2077-8. (14,000X) Tunnel/cave at oxide step (reject).FIGURE 2077-9. (10,000X) Separation of metallization at oxide step (base contact) (accept).METHOD 2077-10. (7,000X) Separation of metallization at contact step (reject).FIGURE 2077-11. (20,000X) Crack-like defect at oxide step (accept).METHOD 2077-12. (7,000X) Crack-like defect at oxide step (reject).FIGURE 2077-13. (7,200X) Thinning at oxide step with more than 50 percent of cross- sectional area remaining at step (multi-level-metal) (accept).METHOD 2077-14. (7,200X) Thinning at oxide step with less than 50 percent of cross- sectional area remaining at step (multi-level-metal) (reject).FIGURE 2077-15. (6,000X) Steep oxide step (MOS) (accept).METHOD 2077-16. (9,500X) Steep oxide step (MOS) (reject).FIGURE 2077-17. (1,000X) Peeling or lifting of contact metallization (reject).METHOD 2077-18. (5,000X) Peeling or lifting of general metallization in contact window area (reject).FIGURE 2077-19. (10,000X) General metallization voids (accept).METHOD 2077-20. (5,000X) General metallization voids (reject).FIGURE 2077-21. (5,000X) Etch-back/undercut type of notch at oxide step (multi-layered-metal) (accept).METHOD 2077-22. (5,000X) Barrier or adhesion layer etch-back/undercut type of notch at oxide step (multi-layered-metal) (accept).FIGURE 2077-23. (11,000X) Shorting/bridging between adjacent metallization areas (reject).METHOD 2077-24. (1,000X) Metallization (microwave device), coverage and alignment good (accept).FIGURE 2077-25. (6,000X) Metallization (microwave device) (accept).METHOD 2077-26. (5,000X) Metallization (400 MHz device) (accept).FIGURE 2077-27. (2,000X) Aluminum discontinuities at base contact dielectric steps - unacceptable base contact and emitter contact coverage microwave device (reject).METHOD 2077-28. (10,000X) Perforated emitter metal finger (microwave device) (reject).FIGURE 2077-29. (20,000X) Base metal finger narrowing (microwave device) (reject).METHOD 2077-30. (5,000X) Metal finger narrowing (4,000 MHz device) (reject).FIGURE 2077-31. (10,000X) Metal undercut at base contact (microwave device) (reject).METHOD 2077-32. (5,000X) Bridging metal and poor base contact coverage (microwave device) (reject).METHOD 2081FORWARD INSTABILITY, SHOCK (FIST)1. Purpose. This test is intended to detect any device discontinuity "ringing" or shifting of the forward dc voltage characteristicmonitored during Apparatus. The shock testing apparatus shall be capable of providing shock pulses of the specified peak acceleration and pulseduration to the body of the device. The acceleration pulse, as determined from the unfiltered output of a transducer with a naturalfrequency greater than or equal to five times the frequency of the shock pulse being established, shall be a half-sine waveform with anallowable distortion not greater than 20 percent of the specified peak acceleration. The pulse duration shall be measured between thepoints at 10 percent of the peak acceleration during rise time and at 10 percent of the peak acceleration during decay time. Absolutetolerances of the pulse duration shall be the greater of ms or 15 percent of the specified duration for specified durations of 2 msand greater. For specified durations less than 2 ms, absolute tolerances shall be the greater of ms or 30 percent of the specifiedduration. The monitoring equipment shall be an oscilloscope or any "latch and hold" interrupt detector of appropriate Procedure. The shock-testing apparatus shall be mounted on a sturdy laboratory table or equivalent base and leveled before device shall be rigidly mounted or restrained by its case with suitable protection for the leads. Special care is required to ensurepositive electrical connection to the device leads to prevent intermittent contacts during shock. The device shall be subjected to fiveshock pulses of 1,000 g peak minimum for the pulse duration of 1 ms in each of two perpendicular planes. For each blow, the carriageshall be raised to the height necessary for obtaining the specified acceleration and then allowed to fall. Means may be provided to preventthe carriage from striking the anvil a second time. With the specified dc voltage and current applied, the forward dc characteristic shall bedisplayed on a oscilloscope swept at 60 Hz and shall be monitored continuously during the shock Failure criteria. During the shock test, any discontinuity, flutter, drift, or shift in oscilloscope trace or any dynamic instabilities shallbe cause for rejection of the semiconductor DUT(s).5. Summary. The following conditions shall be specified in the detail and duration of pulse, if other than that specified (see 3.). and direction of blows, if other than that specified (see 3.). conditions (see 3.).METHOD 20811/2MIL-STD-750DMETHOD 2082BACKWARD INSTABILITY, VIBRATION (BIST)1. Purpose. This test is intended to detect any device discontinuity "ringing" or shifting of the reverse dc voltage characteristicmonitored during Apparatus. The vibration testing apparatus shall be capable of providing the required frequency vibration at the specified monitoring equipment shall be an oscilloscope or any "latch and hold" interrupt detector of appropriate Procedure. The device shall be rigidly fastened on the vibration platform. Special care is required to ensure positive electricalconnection to the device leads to prevent intermittent contacts during vibration. Care must also be exercised to avoid magnetic fields inthe area of the device being vibrated. The device shall be vibrated with a simple harmonic motion at 60 3 Hz, with .1 inch ( mm)minimum double amplitude displacement for a period of 30 seconds minimum in the X orientation planes (see note). The accelerationshall be monitored at a point where the "g" level is equivalent to that of the support point for the device(s). With the specified dc voltageand current applied (for zeners only) and with the specified reverse dc voltage applied (for diodes and rectifiers only), the reverse dccharacteristic shall be displayed on an oscilloscope swept at 60 Hz and shall be monitored continuously during the vibration : g level calculation: g = .0512f2DA. f = frequency in Hz. DA = double amplitude in Failure criteria. During the vibration test, any discontinuity, flutter, drift, or shift in oscilloscope trace or any dynamic instabilitiesshall be cause for rejection of the semiconductor Summary. The following conditions shall be specified in the detail range and time period, if other than that acceleration, if other than that plan, if other than that and lead 20821/2MIL-STD-750DMETHOD PROCEDURES FOR DIODES1. Purpose. This method describes detail procedures and evaluation guidelines for the destructive physical analysis (DPA) ofcommonly specified diodes. It is intended to provide techniques for determining compliance with specified construction requirements, aswell as for evaluating processes, workmanship, and material consistency of the product in relation to MIL-S-19500 Scope. This method pertains to all diode constructions including metal can, except where the die is encapsulated in a packagenormally specified for transistors. Diodes in transistor packages shall be evaluated using method Sampling. Sampling for DPA shall be as specified in the applicable diode detail specification or acquisition procedurerequirements, by contract. Destructive analysis shall be totally compliant with the detail specification for electrical and mechanicalrequirements or as otherwise specified in the acquisition Procedure. The DPA samples shall be subjected to all procedures specified by contract which are applicable to the deviceconstruction. If a device does not conform to the specific requirements herein, or contains systemic anomalies known to directly affectreliability, the disposition of the lot shall be according to contract. Random anomalies detected when devices are subjected to tests orexaminations which are additional, or more rigorous than those in the detail specification, for the product assurance level being inspected,shall be noted in the report but shall not cause the lot to be considered 2101-I Mandatory procedures. 1/TechniquesSeeElectrical testing in accordance with group A, subgroup II of detail testing in accordance with group A, subgroups III and IV and design seal for polymeric encapsulated devices such as bridge assemblies which contain hermetically sealed diodes shall be performed after the removal of the and gas transparent diodes, internal visual lead tensile to analysis51/A list of techniques to be tailored for DPA performance according to the end itemmission requirements and appropriate to the device construction. The testsrequired from this list shall be specified in the of General. DPA status shall be completely documented in a report containing the following required information:a. PIN and MIL-S-19500 reliability Device Lot date When applicable and where acquired, a purchase Sample size for each Results of each Stamp or signature of analyst for each Shipment quantity represented by the Radiographs, one of each required PIND, sample size, and Photographs including one of entire device excluding One copy of electrical One copy of all mechanical dimensions When applicable, MIL-STD-750 test method Destruct sample evidence will remain with Tests. For MIL-S-19500 products, the test methods specified herein shall be performed by specific MIL-S-19500 qualifiedmanufacturers, their customers, or approved sources appearing on the DESC lab suitability Electrical and mechanical verification. A, subgroup 2 inspections for room temperature dc tests shall be performed prior to DPA to verify electrical complianceof the sample. Variables data shall be taken and remain as part of the record for the lot. dimensions as described in the outline drawing shall be measured and recorded when required. Variables data fromincoming or source inspection may be used to satisfy certain requirements of this procedure if the requirements of herein aremet and the contracting parties are in Optional electricals. Optional electrical tests such as subgroup 3 for high and low temperature and subgroup 4 for dynamiccharacteristics may be performed. Additional design capability tests from the detail specification; such as surge current, transient thermalresistance, and temperature coefficient may be performed. These will be specified by the External visual. External visual shall be performed according to method 2071. All text on the device body shall be recorded. If theidentifier BeO is found, the manufacturer shall be contacted for information regarding alternative decap Radiography inspection. Radiographic inspection shall be performed in accordance with method Hermetic seal. Hermetic shall be performed. Devices shall be subject to gross and fine leak in accordance with method the fine leak requirement for double plug construction type diodes. Substitute gross leak, condition E, as applicable, for double plugtypes and method 2068 for double plug opaque glass body types. Paint shall be removed prior to subjecting glass devices to hermeticseal Hermetic seal for polymeric encapsulated devices. Hermetic seal for polymeric encapsulated devices such as bridge assemblieswhich contain hermetically sealed diodes shall have the diodes evaluated after removal of the encapsulant (see herein). PIND testing. PIND testing shall be performed on devices with internal die cavities to method 2052, condition Water vapor testing. Water vapor testing to method 1018 shall be performed on additional unopened devices to one of the threeallowed procedures if it has been determined after delidding (see herein) that corrosion or potentially corrosive elements such aschlorine or potassium salts are present in the Internal visual. Internal visual shall be performed prior to any destructive procedures for diodes of clear glass shall be in accordance with method 2074. Opaque or metal can construction shall be evaluated for internal features after thedecap procedure (see 5. herein). Axial lead tensile test. Axial lead tensile strength shall be tested in accordance with method Resistance to solvents. Resistance to solvents shall be performed in accordance with method Solderability. Solderability shall be performed on "as received" devices within 30 days of receipt according to method 2026. Carein handling shall be exercised to prevent lead surface contamination prior to and during this Terminal strength. Terminal strength shall be performed in accordance with method Decap analysis. Decapping techniques for die inspection and die bond analysis shall be performed. (All inspections requiring anintact diode shall be completed at this point.) Axial lead or surface mount diode shall be encapsulated longitudinally in a mounting compound suitable for use as a carrier for further sampleprocessing. The mounting compound will be selected to have expansion and contraction properties as close as possible tothe device body encapsulant to prevent the generation of stress cracks in sample clear glass construction the sample shall be positioned in such a way that one side of the die is parallel to the sectioningapparatus (see figure 2101-1). This will assure that polishing of the cross section will reveal areas from which approximatedimensions may be sample shall be sectioned using a laboratory grade grinding and lapping table. Precautions shall be taken to preventdamage to the sample by overly aggressive grit paper selection. In the case of cavity type constructions, the process ofgrinding shall stop immediately upon opening the cavity, to allow for the insertion and curing of clear backfilling compoundmaterial. This is done to assure that the internal constituents of the assembly are encased and protected from damage to thedie as the grinding process DPA sample may be polished and stained to enhance construction details at one or several planes. The specimen will berecorded by photomicroscopy when it is determined that the center of the die has been reached (see figure 2101-1). Twophotographs will be taken; one containing means for dimensioning the image, or the optical magnification shall be to the brittle characteristics of the various materials in the construction method, damage may be induced by thesectioning technique. For glass diodes with metallurgical bond, die, or glass cracks damage may be induced as thecompression built into the seal is relaxed as the structure is weakened in the cross sectioning process. This method may notbe used for disposition of metallurgical bond Scribe and break method for glass axial lead and surface mount this method the device is deliberately destroyed to allow visibility to the die attachment diode body is scored circumferentially at the location of the die plane (see figure 2101-2). This is usually accomplishedwith a diamond scribe. The device is then snapped into two pieces. (Observe eye protection against glass particles).Alternatively the glass body may be chemically dissolved and the die snapped. At this time the two plug surfaces may beinspected for both silicon and die metallization silicon remaining on each plug may be chemically removed to provide visibility to the attachment interface materials,however this step is not mandatory. Photographs will be taken of both separated attachment surfaces. A means may beprovided in the photo to dimension the Die bond evaluation. Metallurgically bonded construction types shall be evaluated to the requirements of of separated contact interfaces shall be optically evaluated for the bond area in accordance with table 2101-II (Die attach criteria). If adevice does not satisfy the die attach criteria, as specified, a thermal transient response test (MIL-STD-750, method 3101) shall beperformed, on a sample basis to establish acceptability for 2101-II. Die attach criteria. | Construction| Percent design contact area|| | to be bonded (typical) |||||Category I: Eutectic, thermally matched| 80|||||Category II: Solder| 50|| Silver button with braze 1/| 25|||||Category III: Silver button side| Unspecified|| Back side 2/| 10||||| Zeners d V and schottky| 0|| devices 3/||| | | 1/The silver button design contact area is the entire button top view area in intimatecontact with the plug or braze preform interface. When both sides of the die areadequately bonded, the button to silicon interface (the area from which silver hasgrown, but not including any area which may be expanded over protective oxides)may become the area where separation occurs using the scribe and breaktechnique to open the glass. The button to silicon interface will then become themeasured design contact area. The percent bond area will be determined by thesilicon pulled and remaining on the backside of the button. 2/Silver button construction: The percent area requirement applies only to the backcontact or silicon side. The button to plug interface shall be bonded at point ofcontact or the tangent formed at their interface. 3/The requirements of do not apply for schottky or low voltage thermallymatched noncavity zener Stud mount or axial lead metal internal construction techniques from construction documentation or radiographic crimp construction, encapsulate one device in a specimen mounting compound suitable for grinding, lapping, andpolishing procedures. Section the crimp perpendicular to the longitudinal axis to the point where the crimp is made (asdetermined from the construction details in the drawings or radiographic image) and determine the quality of the mechanicalattachment process (see figure 2101-3). same sample may be used to observe the construction and dimensions of the internal elements. This will beaccomplished by cross section of the device along the longitudinal axis and backfilling the internal cavity with epoxy as soonas the case is penetrated to prevent damage in the grinding operations to follow. Section the device to the approximate centerof the die by carefully examining the device at various planes and reducing the grit abrasiveness to limit sectioning and stain the sample to enhance die construction. Then photograph the internal view all internal surfaces, unmounted samples shall be delidded by cutting the crimp terminal just below the mechanicalattachment then removing the lid by cutting circumferentially with a delidding device above the seating flange (see figure 2101-3). Care must be taken to prevent damage to the post connection at the top of the die when device shall be evaluated for die attachment position, die to preform and header interface, die topography, and post or "C"bend attachment. Photographs of internal construction will be strength testing using method 2037 is optional for construction with metal clips or practical, die shear or punch testing for metal cans shall be in accordance with method Plastic encapsulated devices such as bridges containing several discrete devices shall be evaluated externally for all major features asapplicable and described above for individual construction shall be evaluated by removing the device encapsulating material with appropriate reagents usingstandard laboratory practice. Where uncertainty about the destructiveness of chemicals exists on internal constructionelements, experiments on electrical rejects should occur or the manufacturer should be contacted for diode placement and method of attachment to assembly terminals shall be evaluated. Attention shall be focused oninternal conductor diameters and minimum bridging distance of electrically isolated discrete diodes shall be removed from the assembly in a manner which does not impart mechanical shock orovertemperature conditions. They shall be evaluated according to the method appropriate to their construction as specified inthe appropriate method 2101-1. Axial lead or surface mount 2101-2. Axial lead or surface mount 2101-3. Stud SeriesElectrical characteristics tests for bipolar transistorsMIL-STD-750DMETHOD VOLTAGE, COLLECTOR TO BASE1. Purpose. The purpose of this test is to determine if the breakdown voltage of the device under the specified conditions is greaterthan the specified minimum Test circuit. See figure :The ammeter shall present essentially a short circuit to the terminals between which the current is being measuredor the voltmeter readings shall be corrected for the ammeter 3001-1. Test circuit for breakdown voltage, collector to Procedure. The resistor R1 is a current-limiting resistor and should be of sufficiently high resistance to avoid excessive currentflowing through the device and current meter. The voltage shall be gradually increased, with the specified bias conditions (condition A, B,C, or D) applied, from zero until either the minimum limit for V(BR)CBX or the specified test current is reached. The device is acceptableif the minimum limit for V(BR)CBX is reached before the test current reaches the specified value. If the specified test current is reachedfirst, the device is Summary. The following conditions shall be specified in the detail current (see 3.). condition:A: Emitter to base: Reverse bias (specify bias voltage).B: Emitter to base: Reverse return (specify resistance of R2).C: Emitter to base: Short : Emitter to base: Open BY PULSING1. Purpose. The purpose of this test is to determine the capabilities of the device to withstand Procedure. The device shall be subjected to a pulse or pulses of the length, voltages, currents, and repetition rate specified with thespecified prepulse Summary. The following conditions shall be specified in the detail conditions (see 2.). width (see 2.). voltages and currents (see 2.). rate (see 2.). after of test or number of VOLTAGE,COLLECTOR TO EMITTER1. Purpose. The purpose of this test is to determine if the breakdown voltage of the device under the specified conditions is greaterthan the specified minimum Test circuit. See figure 3011-1. PNP device is shown. For NPN types, reverse the polarities of the voltage and bias sources and zener electronic switch, "S" may be necessary to provide pulses of short duty cycle to minimize the rise of current sensor, or ammeter, shall present essentially a short circuit to the terminals between which the currentis being measured, or the voltage readings shall be corrected is important to prevent, or dampen, potentially damaging oscillations in devices exhibiting negative resistancebreakdown characteristics. Protection can be in the form of a circuit which circumvents the negative resistanceregion, such as one which provides suitable base current as the collector voltage is increased; however, thespecified bias condition and test current must be applied when the voltage is measured. Additional protection canbe provided with a zener diode, or transient voltage protection circuit to limit to collector voltage at, or slightly above,the specified minimum of the protection used, extreme care must be exercised to ensure the collector current and junctiontemperature remain at a safe value, as given in the applicable device 3011-1. Test circuit for breakdown voltage, collector to Procedure. The resistor R1 is a current-limiting resistor and should be of sufficiently high resistance to avoid excessive currentflowing through the device and current sensor. The voltage shall be increased, with the specified bias conditions (condition A, B, C, or D)applied, until the specified test current is reached. The device is acceptable if the voltage applied at the specified test current is greaterthan the minimum limit for V(BR) of 2MIL-STD-750D4. Summary. The following conditions shall be specified in the detail current (see 3.). cycle and pulse width, when required (see note 1 above). condition as follows:A: Emitter to base: Reverse bias (specify bias voltage).B: Emitter to base: Resistance return (specify resistance value of R2).C: Emitter to base: Short : Emitter to base: Open 3015DRIFT1. Purpose. The purpose of this test is to determine the drift of a parameter specified in the detail specification of the Apparatus. The apparatus used for the performance of the drift test shall be the same as that utilized for testing the Procedure. The voltages and currents specified in the detail specification shall be applied. In the period from 10 seconds to 1minute, the measurement specified in the detail specification shall drift no more than the amount specified in the detail Summary. The following conditions shall be specified in the detail currents and voltages (see 3.). parameter (see 3.). apparatus or test circuit (see 2.).METHOD 30151/2MIL-STD-750DMETHOD 3020FLOATING POTENTIAL1. Purpose. The purpose of this test is to measure the dc potential between the specified, open-circuited terminal and referenceterminal when a dc potential is applied to the other specified Test circuit. See figure :The circuit shown is for measuring the emitter floating potential. For other device configurationsthe above circuitry should be modified in such a manner that is capable of demonstrating deviceconformance to the minimum requirements of the individual 3020-1. Test circuit for floating Procedure. The specified dc voltage shall be applied to the specified terminals and the dc voltage of the open-circuited terminal andreference terminal shall be Summary. The following conditions shall be specified in the detail voltage (see 3.). resistance of high impedance voltmeter (see figure 3020-1). voltage application and reference terminals (see 3.).METHOD 30201/2MIL-STD-750DMETHOD VOLTAGE, EMITTER TO BASE1. Purpose. The purpose of this test is to determine if the breakdown voltage of the device under the specified conditions is greaterthan the specified minimum Test circuit. See figure 3026-1. NOTE:The ammeter shall present essentially a short circuit to the terminals between which the current isbeing measured or the voltmeter readings shall be corrected for the ammeter 3026-1. Test circuit for breakdown voltage, emitter to Procedure. The resistor R1 is a current-limiting resistor and should be of sufficiently high resistance to avoid excessive currentflowing through the device and current meter. The voltage shall be gradually increased, with the specified condition (A, B, C, or D)applied, from zero until either the minimum limit for V(BR)EBX or the specified test current is reached. The device is acceptable if theminimum limit for V(BR)EBX is reached before the test current reaches the specified value. If the specified test current is reached first,the device is Summary. The following conditions shall be specified in the detail current (see 3.). condition:A: Collector to base: Reverse bias (specify bias voltage).B: Collector to base: Resistance return (specify resistance of R2).C: Collector to base: Short : Collector to base: Open 3030COLLECTOR TO EMITTER VOLTAGE1. Purpose. The purpose of this test is to measure the voltage between the collector and emitter of the device under Test circuit. See figure 3030-1. Test circuit for collector to emitter Procedure. The bias supplies shall be adjusted until the specified voltages and currents are achieved. The voltage between thecollector and emitter shall then be measured. If high current values are to be used in this measurement, suitable pulse techniques maybe used to provide pulses of short duty cycle to minimize the rise in junction Summary. The following conditions shall be specified in the detail voltages and currents (see 3.). cycle and pulse width if applicable (see 3.).METHOD 30301/2MIL-STD-750DMETHOD TO BASE CUTOFF CURRENT1. Purpose. The purpose of this test is to measure the cutoff current of the device under the specified Test circuit. See figure 3036-1. NOTE:The ammeter shall present essentially a short circuit to the terminals between which the current is being measured orthe voltmeter shall be corrected for the drop across the 3036-1. Test circuit for collector to base cutoff Procedure. The specified dc voltage shall be applied between the collector and the base with the specified bias condition (A, B, C,or D) applied to the emitter. The measurement of current shall be made at the specified ambient or case Summary. The following conditions shall be specified in the detail voltage (see 3.). temperature if other than +25 C 3 C and whether case or ambient (see 3.). condition:A: Emitter to base: Reverse bias (specify bias voltage).B: Emitter to base: Resistance return (specify resistance of R2).C: Emitter to base: Short : Emitter to base: Open TO EMITTER CUTOFF CURRENT1. Purpose. The purpose of this test is to measure the cutoff current of the device under the specified Test circuit. See figure :The ammeter shall present essentially a short circuit to the terminals between which the current is being measured orthe voltmeter shall be corrected for the drop across the 3041-1. Test circuit for collector to emitter cutoff Procedure. The specified voltage shall be applied between the collector and emitter with the specified bias condition (A, B, C, or D)applied to the base. The measurement of current shall be made at the specified ambient or case Summary. The following conditions shall be specified in the detail voltage (see 3.). temperature if other than +25 C 3 C and whether case or ambient (see 3.). condition:A: Emitter to base: Reverse bias (specify bias voltage).B: Emitter to base: Resistance return (specify resistance value of R2).C: Emitter to base: Short : Emitter to base: Open 3051SAFE OPERATING AREA (CONTINUOUS DC)1. Purpose. The purpose of this test is to verify the boundary of the SOA of a transistor as constituted by the interdependency of thespecified voltage, current, power, and temperature in a temperature stable Test circuit. See figure 3051-1. Test circuit for SOA (continuous dc).3. with VCC and VEE at a low value, increase VCC to approximately obtain specified VCE. Increase VEE toapproximately obtain specified IC. Increase VCC and subsequently adjust VEE to obtain specified VCE and IC. Operate thetransistor at the specified temperature and for the specified time VCC to obtain VCE near zero. Turn off VEE. Turn off transistor shall be considered a failure if IC varies 10 percent during operation, or exceeds the end Summary. The following conditions shall be specified in the detail SOA graph: IC versus VCE (see 3.). , case or ambient (see 3.). of VCE and time (see 3.). after 30511/2MIL-STD-750DMETHOD 3052SAFE OPERATING AREA (PULSED)1. Purpose. The purpose of this test is to verify the capability of a transistor to withstand pulses of specific voltage, current and time,establishing a Test circuit. See figure 3052-1. Test circuit for SOA (pulsed).3. Procedure. Starting at a low value, adjust VBB2 and VCC to the specified levels. With the duty cycle and pulse width preset tospecified conditions, increase VBB1 voltage to achieve the specified Summary. The following conditions shall be specified in the detail SOA graph: IC versus , case or pulse and bias conditions:(1)Pulse duty cycle.(2)Pulse width.(3)tr and tf.(4)Values for RBB2, RBB1, and VBB2 (see figure 3052-1).(5)Number of pulses or test of RE, VCC, and IC (see 3.). after 30521/2MIL-STD-750DMETHOD 3053SAFE OPERATING AREA (SWITCHING)1. Purpose. The purpose of this test is to verify the capability of a transistor to withstand switching between saturation and cut-off forvarious specified loads, establishing a Test circuit. See figure 3053-1. Test circuit for SOA (switching).3. Procedure. The output load circuit configuration shall be as specified (condition A, B, or C). Starting at a low value, adjust VBB2and VCC to the specified levels. With the duty cycle and repetition rate preset to specified conditions, increase VBB1 voltage to achievethe specified IC; and the output waveform (IC versus VCE) shall be observed on the scope. When the transistor is turned off (switched),the observed trace shall be a smooth curve between saturation and cut-off. Any oscillations or inconsistencies on the trace shall because for Summary. The following conditions shall be specified in the detail SOA graph, with parameter coordinates as follows:(1)IC versus VCE for load condition A.(2)IC versus VCE for load condition B.(3)IC versus L as functions of RBB2 and VBB2, for load condition condition as follows:A: Resistive : Clamped inductive : Unclamped inductive , case or 30531 of pulse and bias conditions:(1)Number of pulses or test duration.(2)Pulse width.(3)Pulse duty cycle.(4)tr and tf.(5)RBB1 and VBB1.(6)RBB2 and conditions for load and output bias:Condition A:Values of RL, IC, and B:Values of RL, IC, VCC, diode type or characteristics, inductance and dc resistance of C:Values of IC, VCC, and characteristics of inductor L including its inductance, "Q", dc resistance, andresonant after 30532MIL-STD-750DMETHOD TO BASE CUTOFF CURRENT1. Purpose. The purpose of this test is to measure the cutoff current of the device under the specified Test circuit. See figure :The ammeter shall present essentially a short circuit to the terminals between which the current is being measured orthe voltmeter shall be corrected for the drop across the 3061-1. Test circuit for emitter to base cutoff Procedure. The specified direct current voltages shall be applied between the emitter and the base with the specified bias condition(condition A, B, C, or D) applied to the collector. The measurement of current shall be made at the specified ambient or Summary. The following conditions shall be specified in the detail voltage (see 3.). temperature if other than +25 C 3 C and whether case or ambient (see 3.). condition (A, B, C, or D):A: Collector to base: Reverse bias (specify bias voltage).B: Collector to base: Resistance return (specify resistance of R2).C: Collector to base: Short : Collector to base: Open EMITTER VOLTAGE (SATURATED OR NONSATURATED)1. Purpose. The purpose of this test is to measure the base to emitter voltage of the device in either a saturated or Test circuit. Circuit and procedure shown are for base to emitter. For other parameters the circuit and procedure should bechanged : If necessary, switch S shall be used to provide pulses of short- duty cycle to minimize therise in junction temperature. When pulsing techniques are used, oscillograph methods shall be usedto measure VBE and the other necessary parameters, and the duty cycle and pulse width shall 3066-1. Test circuit for base emitter voltage (saturated or nonsaturated).3. Test condition A (saturated). The resistor R1 shall be made large. If the pulse method is used, the resistor R2 shall be chosen incombination with VCC so that the specified collector current is achieved at a value of VCC low enough to ensure that the device will notbe operated in breakdown between pulses. If the pulse method is not used, resistor R2 can be any convenient value. The current IB andvoltage VCC shall be adjusted until IB and IC achieve their specified values. Then, VBE = VBE(sat). Test condition B (nonsaturated). For this test resistor R2 shall be zero. The specified values of IB and VCE shall be applied. VBE is then measured. Alternately, the specified VCE shall be applied and IB adjusted to obtain the specified Summary. The following conditions shall be specified in the detail cycle and pulse width, when condition letter (see 3.). voltages or currents (see 3.). to be 3071SATURATION VOLTAGE AND RESISTANCE1. Purpose. The purpose of this test is to measure the saturation voltage and resistance of the device under the specified Test circuit. Circuit and procedure shown are for collector to emitter. For other parameters the circuit and procedure should bechanged : If necessary, switch S shall be used to provide pulses of short- duty cycle tominimize the rise in junction temperature. When pulsing techniques are used,oscillograph methods shall be used to measure VBE and the other necessaryparameters, and the duty cycle and pulse width shall be 3071-1. Test circuit for saturation voltage and Procedure. The resistor R1 shall be made large. If the pulse method is used, resistor R2 shall be chosen in combination with VCCso that the specified collector current may be achieved at a value of VCC which is low enough to ensure that the device is not operated inbreakdown between pulses. If pulse methods are not used R2 may be any convenient value. The current IB and VCC shall be adjusteduntil IB and IC achieve their specified values. VCE(sat) is then equal to the voltage measured by voltmeter VCE under the specifiedconditions. Saturation resistance may be determined from the same circuit conditions, as follows:4. Summary. The following conditions shall be specified in the detail cycle and pulse width, when required (see 3.). voltages or currents (see 3.). to be 30711/2MIL-STD-750DMETHOD TRANSFER RATIO1. Purpose. The purpose of this test is to measure the forward-current transfer ratio of the device under the specified Test circuit. Circuit and procedure shown are for common emitter. For other parameters the circuit and procedure should bechanged accordingly. NOTE:The ammeter shall present essentially a short circuit to the terminals between which the current isbeing measured or the voltmeter shall be corrected for the drop across the 3076-1. Test circuit for forward-current transfer Procedure. The voltage VCE shall be set to the specified value and the current IB shall be adjusted until the specified current IC isachieved. ICThen, hFE = --- IBIf high-current values are to be used in this measurement, switch S shall be used to provide pulses of short-duty cycle to minimize therise in junction temperature. When pulsing techniques are used, oscillograph methods may be used to measure IC and Summary. The following conditions shall be specified in the detail voltage or current (see 3.). cycle and pulse width, when required (see 3.). to be INPUT RESISTANCE1. Purpose. The purpose of this test is to measure the input resistance of the device under the specified Test circuit. Circuit and procedure shown are for common emitter. For other parameters the circuit and procedure should bechanged accordingly. NOTE:If necessary, switch S shall be used to provide pulses of short-duty cycle tominimize the rise in junction temperature. When pulsing techniques are used,oscillograph methods shall be used to measure VBE and other necessaryparameters, and the duty cycle and pulse width shall be 3086-1. Test circuit for static input Procedure. The resistor R1 shall be made large. If the pulse method is used, resistor R2 shall be chosen in combination with VCCso that the specified collector current is achieved at a value of VCC low enough to ensure that the device will not be operated inbreakdown between pulses. If the pulse method is not used, resistor R2 can be any convenient value. The current IB and VCC shall beadjusted until IB and IC achieve their specified Summary. The following conditions shall be specified in the detail duty cycle and width, when required (see 3.). voltages or currents (see 3.). to be TRANSCONDUCTANCE1. Purpose. The purpose of this test is to measure the static transconductance of the device under the specified Test circuit. See figure 3092-1. NOTE:For other configurations, the circuit may be modified in such a manner that it is capable of demonstratingdevice conformance to the minimum requirements of the individual 3092-1. Test circuit for static Procedure. The resistor R1 shall be made large or the voltage source VBB shall be replaced by a constant current source. Theresistor R2 shall be chosen in combination with VCC so that the specified collector current is achieved at a value of VCC which is lowerthan V(BR)CEO. The current IB shall be adjusted until VCE and IC achieve their specified values. The current IC or IE and the voltagesVBE, VBC, or VEB shall then be measured. Using the values obtained through these measurements, the static transconductance shallbe calculated as follows:If high current values are to be used in the measurement, suitable pulse techniques may be used to provide pulses of short-duty cycleto minimize the rise in junction Summary. The following conditions shall be specified in the detail voltage or cycle and pulse width, if SeriesCircuit-performance and thermal-resistance measurementsFor thermal-resistance measurements, at least three temperature sensitive parameters (TSP) of the transistor can be used; thecollector to base cutoff current, ICBO; the forward voltage drop of the emitter to base diode, VEB; and the forward voltage drop ofthe collector to base diode, VCB. The methods described in this standard refer to the thermal resistance between specifiedreference points of the device. For this type of measurement, power is applied to the device at two values of case, ambient, orother reference point temperature, such that identical values of ICBO, VEB, or VCB are read during the cooling portion of IMPEDANCE TESTING OF DIODES1. Purpose. The purpose of this test is to determine the thermal performance of diode devices. This can be done in two ways,steady-state thermal impedance or thermal transient testing. Steady-state thermal impedance (referred to as thermal resistance)determines the overall thermal performance of devices. A production-oriented screening process, referred to as thermal transient testing,is a subset of thermal impedance testing and determines the ability of the diode chip-to-header interface to transfer heat from the chip tothe header, and is a measure of the thermal quality of the die attachment. It is relevant to designs which use headers, or heat conductingplugs, with mass and thermal conductivity allowing effective discrimination of poor die attachments. This is particularly true with powerdevices. The method can be applied to rectifier diodes, transient voltage suppressors, power zener diodes, and some zener, signal andswitching diodes. This method is intended for production monitoring, incoming inspection, and pre-burn in screening Background and scope for thermal transient testing. Steady-state thermal response (thermal resistance) and thermal transientresponse (related to and often called thermal impedance or thermal transient impedance) of semiconductor devices are sensitive to thepresence of these voids in the die attachment material between the semiconductor chip and package since voids impede the flow of heatfrom the chip to the substrate (package). Due to the difference in the thermal time constants of the chip and package, the measurementof transient thermal response can be made more sensitive to the presence of voids than can the measurement of steady-state thermalresponse. This is because the chip thermal time constant is generally several orders of magnitude shorter than that of the , the heating power pulse width can be selected so that only the chip and the chip-to-substrate interface are heated during the pulseby using a pulse width somewhat greater than the chip thermal time constant but less than that of the substrate. Heating power pulsewidths ranging from 1 to 400 ms for various package designs have been found to satisfy this criterion. This enables the detection ofvoids to be greatly enhanced, with the added advantage of not having to heatsink the DUT. Thus, the transient thermal responsetechnique is less time-consuming than the measurement of thermal resistance for use as a manufacturing screen, process control, orincoming inspection measure for die attachment integrity Definitions. The following symbols and terminology shall apply for the purpose of this test :The forward biased junction voltage of the DUT used for junction temperature :The initial VF value before application of heating :The final VF value after application of heating 'VF:The change in the TSP, VF, due to the application of heating power to the :The current applied to the DUT during the heating time in order to cause power :The heating voltage resulting from the application of IH to the :The heating power pulse magnitude; product of VH and :The duration of PH applied to the :The measurement current used to forward bias the temperature sensing diode junction for measurement of :Measurement delay time is defined as the time from the start of heating power (PH) removal to the start of the final VF measurement time, referred to as of :Sample window time during which final VF measurement is made. The value of tSW should be small; it canapproach zero if an oscilloscope is used for manual :Voltage-temperature coefficient of VF with respect to TJ at a fixed value of IM; in :Thermal calibration factor equal to the reciprocal of VTC; in :The comparison unit, consisting of 'VF divided by VH, that is used to normalize the transient thermal response forvariations in power dissipation; in units of TJ:The DUT junction 'TJ:The change in TJ caused by the application of PH for a time equal to :Thermal impedance from device junction to a time defined reference point; in units of :Thermal impedance from device junction to a point on the outside surface of the case immediately adjacent to thedevice chip measured using time equal time constant of device; in units of :Thermal resistance from device junction to a defined reference point; in units of qC/W. (Also shown as TJX inpublications.)RTJC: Thermal resistance from device junction to a point on the outside surface of the case immediately adjacent to thedevice chip; in units of qC/W. (Also shown as TJC in publications.)RTJA:Thermal resistance from device junction to an ambient (world); in units of qC/W. (Also shown as TJA in publications.)3. Apparatus. The apparatus required for this test shall include the following, configured as shown on figure 3101-1, as applicable tothe specified test constant current source capable of adjustment to the desired value of IH and able to supply the VH value required by theDUT. The current source should be able to maintain the desired current to within r2 percent during the entire length ofheating constant current source to supply IM with sufficient voltage compliance to turn the TSP junction fully electronic switch capable of switching between the heating period conditions and measurement conditions in a time frameshort enough to avoid DUT cooling during the transition; this typically requires switching in the microsecond or tens ofmicroseconds voltage measurement circuit capable of accurately making the VFf measurement within the time frame with 3101-1. Thermal impedance testing setup for Test General description. The test begins with the adjustment of IM and IH to the desired values. The value of IH is usually at least 50times greater than the value of IM. Then with the electronic switch in position 1, the value of VFi is measured. The switch is then movedto position 2 for a length of time equal to tH and the value of VH is measured. Finally, at the conclusion of tH, the switch is again movedto position 1 and the VFf value is measured within a time period defined by tMD (or tMD + tSW, depending on the definitions statedpreviously). The two current sources are then turned off at the completion of the voltage and current waveforms for all three time periods of the test are shown below on figure 3101-2. Thermal impedance testing test equipment may provide a 'VF directly instead of VFi and VFf; this is an acceptable alternative. Record the value of' test equipment may provide TJX directly instead of VFi and VFf for thermal resistance calculations; this is anacceptable alternative. Record the value of waveforms, as may be generated by ATE using the general principles of this method, may be used upon approvalof the qualifying Acceptance General discussion. Variations in diode characteristics from one manufacturer to another cause difficulty in establishing a singleacceptance limit for all diodes tested to a given specification. Ideally, a single acceptance limit value for 'VF would be the simplestapproach. However, different design, materials, and processes can alter the resultant 'VF value for a given set of test conditions. Listedbelow are several different approaches to defining acceptance limits. The 'VF limit is the simplest approach and is usually selected forscreening purposes. through require increasingly greater detail or 'V limit. A single 'VF limit is practical if the K factor and VH values for all diodes tested to a given specification are Fnearly identical. Since these values may be different for different manufacturers, the use of different limits is likely to more accuratelyachieve the desired intent. (A lower limit does not indicate a better die bond when comparing different product sources.) The diodespecifications would list the following test conditions and measurement parameters:IH (in A)tH (in ms)IM (in mA)tMD (in Ps)tSW (in Ps) VF (maximum limit value, in mV) 'T limit. (Much more involved than 'V , but useful for examining questionable devices.) Since 'TJ is the product of K J F(in accordance with 6.) and 'VF, this approach is the same as defining a maximum acceptable junction temperature rise for a given set oftest CU limit. (Slightly more involved than 'TJ.) The 'TJ limit approach described above does not take into account potential powerdissipation variations between devices. The VH value can vary, depending on chip design and size, thus causing the power dissipationduring the heating time to be different from device to device. This variation will be small within a lot of devices produced by a singlemanufacturer but may be large between manufacturers. A CU limit value takes into account variations in power dissipation due todifferences in VH by dividing the 'VF value by (KxCU) limit. (Slightly more involved but provides greater detail.) This is a combinational approach that takes into account both Kfactor and power dissipation variations between Z limit. (For full characterization; not needed for screening purposes.) The thermal impedance approach uses an TJXabsolute magnitude value specification that overcomes the problems associated with the other approaches. Thermal impedance is timedependent and is calculated as R limit. (For thermal resistance specification testing.) The thermal resistance to some defined point, such as the case, TJXis an absolute magnitude value specification used for equilibrium conditions. The tH heating time must therefore be extended toappreciably longer times (typically 20 to 50 seconds). In the example of RTJC measurements, the case must be carefully stabilized andmonitored in temperature which requires an infinite heat sink for optimum results. The 'TJ is the difference in junction temperature to thecase temperature for the example of General comment for thermal transient testing. One potential problem in using the thermal transient testing approach lies in tryingto make accurate enough measurements with sufficient resolution to distinguish between acceptable and nonacceptable diodes. As thediode-under-test current handling capability increases, the thermal impedance under transient conditions will become a very small raises the potential for rejecting good devices and accepting bad ones. Higher IH values must be used in this Measurement of the TSP V . The calibration of VF versus TJ is accomplished by monitoring VSD for the required value of FIM as the environmental temperature (and thus the DUT temperature), and is varied by external heating. It is not required if theacceptance limit is 'VF (see ), but is relevant to the other acceptance criteria (see through ). The magnitude of IM shall bechosen so that VF is a linearly decreasing function over the normal TJ range of the device. IM must be large enough to ensure that thediode junction is turned on but not large enough to cause significant self-heating. An example of the measurement method and resultingcalibration curve is shown on figure MIL-STD-750D Step 1: Measure VF1 at TJ1 using IM Step 2: Measure VF2 at TJ2 using IM Step 3: IM: must be large enough to overcome surface leakage effects but small enough not to cause significant self-heating. TJ: is externally applied: ( , via oven, liquid) 3101-3. Example curve of V versus T . F JA calibration factor K (which is the reciprocal of the slope of the curve on figure 3101-3) can be defined as:It has been found experimentally that the K-factor variation for all devices within a given device type class is small. The usual procedureis to perform a K factor calibration on a 10 to 12 piece sample from a device lot and determine the average K and standard deviation (V).If V is less than or equal to three percent of the average value of K, then the average value of K can be used for all devices within the V is greater than three percent of the average value of K, then all the devices in the lot shall be calibrated and the individual values of Kshall be used in determining device MIL-STD-750D7. Establishment of test conditions and acceptance limits. Thermal resistance measurements require that IH be equal to the requiredvalue stated in the device specifications, typically at rated current or higher. Values for tH, tMD, and heat sink conditions are also takenfrom the device specifications. The steps shown below are primarily for thermal transient testing and thermal characterization following steps describe how to set up the test conditions and determine the acceptance limits for implementing the transient thermaltest for die attachment evaluation using the apparatus and definitions stated Initial device testing procedure. The following steps describe in detail how to set up the apparatus described previously for propertesting of various diodes. Since this procedure thermally characterizes the diode out to a point in heating time required to ensure heatpropagation into the case ( , the TJX condition), an appropriate heat sink should be used or the case temperature should be 1:From a 20 to 25 piece sample, pick any one diode to start the setup process. Set up the test apparatus as follows:IH = A(Or some other desired value near the DUTs normal operating current.)tH = 10-50 msUnless otherwise specified, for most devices rated up to 15 W power - 100 msUnless otherwise specified, for most devices rated up to 200 W power 250 msFor steady state thermal resistance measurement. The pulse must be shown to correlate tosteady state conditions before it can be substituted for steady state = 100 Ps maxA larger value may be required on power devices with magnetic package elements whichgenerate nonthermally induced transients; unless otherwise specified, this would beobserved in the t3 region of figure = 10 mA(Or some nominal value approximately two percent, or less, of IH.)Step 2:Insert device into the apparatus test fixture and initiate a test. (For best results, a test fixture that offers some form ofheat sinking would be desirable. Heat sinking is not needed if either the power dissipation during the test is well withinthe diode's free-air rating or the maximum heating time is limited to less than that required for the heat to propagatethrough the case.)Step 3:If 'VF is in the 5 to 80 mV range, then proceed to the next step. This range approximately corresponds to a junctiontemperature change of roughly +10qC to +20qC and is sufficient for initial comparison 'VF is less than 5 mV, return to step 1 and increase heating power into device by increasing VF is greater than 80 mV, approximately corresponding to a junction temperature change greater than +40qC, itwould probably be desirable to reduce the heating power by returning to step 1 and reducing IH. NOTE:The test equipment shall be capable of resolving VF to within five percent. If not, the higher value of VF must beselected until the five percent tolerance is :Two different devices can have the same junction temperature rise even when PH is different, due to widelydiffering VH. Within a given lot, however, a higher VH is more likely to result in a higher junction temperature such examples, this screen can be more accurately accomplished using the CU value. As defined in 2., CUprovides a comparison unit that takes into account different device VH values for a given IH test 4:Test each of the sample devices and record the VF and CU 5:Select out the devices with the highest and lowest values of CU and put the remaining devices VF values can be used instead of CU if the measured values of VH are very tightly grouped around the 6:Using the devices from step 5, collect and plot the heating curve data for the two devices in a manner similar to theexamples shown on figure 7:Interpretation of the heating curves is the next step. Realizing that the thermal characteristics of identical chips shouldbe the same if the heating time (tH) is less than or equal to the thermal time constant of the chip, the two curves shouldstart out the same for the low values of tH. Nonidentical chips (thinner or smaller in cross section) will have completelydifferent curves, even at the smaller values of tH. As the value of tH is increased, thereby overcoming the chip thermalconstant, heat will have propagated through the chip into the die attachment region. Since the heating curve devices ofstep 5 were specifically chosen for their difference, the curves of figure 3101-4 diverge after tH reaches a value wherethe die attachment variance has an affect on the device junction temperature. Increasing tH further will probably resultin a flattening of the curve as the heating propagates in the device package. If the device package has little thermalmass and is not well mounted to a good heat sink, the curve will not flatten very much, but will show a definite change 8:Using the heating curve, select the appropriate value of tH to correspond to the inflection point in the transition regionbetween heat in the chip and heat in the there are several different elements in the heat flow path: Chip, die attachment, substrate, substrate attach, andpackage for example in a hybrid, there will be several plateaus and transitions in the heating curve. Appropriateselection of tH will optimize evaluation sensitivity to other attachment 9:Return to the apparatus and set tH equal to the value determined from step 3101-4. Heating curves for two extreme 10:Because the selected value of tH is much less than that for thermal equilibrium, it is possible to significantly increasethe heating power without degrading or destroying the device. The increased power dissipation within the DUT willresult in higher VF or CU values that will make determination of acceptable and nonacceptable devices much 11:The pass/fail limit, the cut-off point between acceptable and nonacceptable devices, can be established in a variety to other die attachment evaluation methods, such as die shear and x-ray, while these two methodshave little actual value from a thermal point of view, they do represent standardization methods as described invarious military allowable junction temperature variations between devices, since the relationship between 'TJ and 'VF is about , the junction temperature spread between devices can be easily determined. The TJpredicts reliability. Conversely, the TJ spread necessary to meet the reliability projections can be translated to a'VF or CU value for pass/fail fully utilize this approach, it will be necessary to calibrate the devices for the exact value of the TJ to VFcharacteristic. The characteristic's slope, commonly referred to as K factor, is easily measured on a samplebasis using a voltmeter, environmental chamber, temperature indicator, and a power supply setup for forcing,temperature indicator, and a power supply setup as described in 6. A simple set of equations yield the junctiontemperature once K and 'VF are known:'TJ = (K) ('VF)TJ = TA + 'TJWhere TA is the ambient or reference temperature. For thermal transient test conditions, this temperature isusually equivalent to lead temperature (TL) for axial lead devices or case temperature (TC) for case from a 20 to 25 device sample; the distribution of 'VF or CU values should be a normal one withdefective devices out of the normal range. Figure 3101-5 shows a 'VF distribution for a sample lot of : The left-hand side of the histogram envelope is fairly well defined but the other side is greatly skewed tothe right. This comes about because the left-hand side is constrained by the absolutely best heat flow that canbe obtained with a given chip assembly material and process. The other side has no such constraints becausethere is no limit as to how poorly a chip is 3101-5. Typical V distribution. F The usual rule of thumb in setting the maximum limit for 'VF or CU is to use the distribution average value and one standarddeviation (V). For example:('VF) | = 'VF + X V ' | high limit(CU) | = CU + X V ' | high limitWhere X = 3 in most statistical data required is obtained by testing 25 or more devices under the conditions of step maximum limit determined from this approach should be correlated to the diode's specified thermal will ensure that the 'VF or CU limits do not pass diodes that would fail the thermal resistance 12:Once the test conditions and pass/fail limit have been determined, it is necessary only to record this information forfuture testing requirements of the same device in the same steps listed hereto are conveniently summarized in table 3101-I. Summary of test procedure steps. ||||| General description| Steps| Comments|| | | ||||||| A | Initial setup| 1 through 4| Approximate instrument settings to find||||| variations among devices in 10 to 15 piece||||| sample.|| | | | ||||||| B | Heating curve| 5 through 6| Using highest and lowest reading devices,||| generation|| generate heating curves.|| | | | ||||||| C | Heating curve| 7 through 9| Heating curve is used to find more||| interpretation|| appropriate value for tH corresponding to||||| heat in the die attachment area (or some||||| other desired interface in the heat flow||||| path).|| | | | ||||||| D | Final setup| 10| Heating power applied during tH is||||| increased in order to improve measurement||||| sensitivity to variations among devices.|| | | | ||||||| E | Pass-fail| 11 through 12| A variety of methods is available for||| determination|| setting the fall limit; the statistical||||| approach is the fastest and easiest to||||| implement.|| | | | | Routine device thermal transient testing procedure. Once the proper control settings have been determined for a particular devicetype from a given manufacturing process or vendor, repeated testing of that device type simply requires that the same test conditions beused as previously device types or the same devices manufactured with a different process will require a repeat of for proper thermal transient Test conditions and measurements to be specified and Thermal transient and equilibrium Test conditions. Specify the following test measuring current heating current heating time measurement time delay sample window time PsMETHOD Data. Record the following initial forward voltage heating voltage final forward voltage V(NOTE:Some test equipment may provide a 'VF instead of VFi and VFf; this is an acceptable alternative. Record the value of' test equipment may provide direct display of calculated CU or TJX; this is an acceptable alternative. Record thevalue of CU or TJX.) K factor calibration. (Optional for criteria or , mandatory for , , or ) Test conditions. Specify the following test current magnitude junction temperature VF voltage junction temperature VF voltage K factor. Calculate K factor in accordance with the following equation:K factor Specification limit calculations. One or more of the following should be measured or calculated, as called for on the devicespecification (see ):a. VF mV/Vc. TJ qC/WMETHOD MIL-STD-750DMETHOD 3103THERMAL IMPEDANCE MEASUREMENTS FORINSULATED GATE BIPOLAR TRANSISTORS(DELTA GATE-EMITTER ON VOLTAGE METHOD)1. Purpose. The purpose of this test method is to measure the thermal impedance of the IGBT under the specified conditions ofapplied voltage, current, and pulse duration. The temperature sensitivity of the gate-emitter ON voltage, under conditions of appliedcollector-emitter voltage and low emitter current, is used as the junction temperature indicator. This method is particularly suitable toenhancement mode, power IGBTs having relatively long thermal response times. This test method is used to measure the thermalresponse of the junction to a heating pulse. Specifically, the test may be used to measure dc thermal resistance and to ensure proper diemountdown to its case. This is accomplished through the appropriate choice of pulse duration and heat power magnitude. Theappropriate test conditions and limits are detailed in Definitions. The following symbols and terms shall apply for the purpose of this test :Emitter current applied during measurement of the gate-emitter ON :Heating current through the collector or emitter VH:Heating voltage between the collector and of the heating power pulse applied to DUT in watts; the product of IH and :Heating time during which PH is :Voltage-temperature coefficient of VGE(ON) with respect to TJ; in :Thermal calibration factor equal to reciprocal of VTC; in :Junction temperature in degrees :Junction temperature in degrees Celsius before start of the power :Junction temperature in degrees Celsius at the end of the power :Reference temperature in degrees :Initial reference temperature in degrees :Final reference temperature in degrees (ON):Gate-emitter ON voltage in (ON)i:Initial gate-emitter ON voltage in (ON)f:Final gate-emitter ON in (M):Gate-emitter voltage during measurement (H):Gate-emitter voltage during heating (M):Collector-emitter voltage during measurement (H):Collector-emitter voltage during heating VCG:Collector-gate voltage, adjusted to provide appropriate 31031 of :Measurement delay time is defined as the time from the removal of heating power PH to the start of the VGE(ON) :Sample window time during which final VGE(ON) measurement is :Transient junction-to-reference point thermal impedance in C/W. Z4JX or specified power pulse duration is:Where: 'Tx = change in reference point temperature during the heating pulse (see and for short heating pulses, , die attach evaluation, this term is normally negligible.)3. Apparatus. The apparatus required for this test shall include the following as applicable to the specified test Case temperature measurement. A thermocouple for measuring the case temperature at a specified reference point. Therecommended reference point shall be located on the case under the heat source. Thermocouple material shall be copper- constantan(type T) or equivalent. The wire size shall be no larger than AWG size 30. The junction of the thermocouple shall be welded, rather thansoldered or twisted, to form a bead. The accuracy of the thermocouple and its associated measuring system shall be C. Propermounting of the thermocouple to ensure intimate contact to the reference point is critical for system Controlled temperature environment. A controlled temperature environment capable of maintaining the case temperature duringthe device calibration procedure to within 1 C over the temperature range of +23 C to +100 C, the recommended temperatures formeasuring K factor calibration. A K factor calibration setup, as shown on figure 3103-1, that measures VGE(ON) for the specified values ofVCE and IM in an environment where temperature is both controlled and measured. A temperature controlled circulating fluid bath isrecommended. The current source must be capable of supplying IM with an accuracy of 2 percent. The voltage source VCG isadjusted to supply VCE with an accuracy of 2 percent. The voltage measurement of VGE(ON) shall be made with a voltmeter capableof 1 mV resolution. The device-to-current source wire size shall be sufficient to handle the measurement current (AWG size 22 strandedis typically used for up to 100 mA).FIGURE 3103-1. K factor calibration 31032 Thermal testing. There are two approaches to the actual thermal testing, either the common-gate or the common-source methods work equally well, although the common-source method may be more reliable and less potentially damaging to the figures and description below describe the thermal measurement for n-channel enhancement mode devices. Opposite polaritydevices can be tested by appropriately reversing the various supplies. Depletion mode devices can be tested by applying the gate-emittervoltage (VGE) in the appropriate Common-gate thermal test circuit. A common-gate configuration test circuit used to control the device and to measure thetemperature using the gate-emitter ON voltage as the temperature sensing parameter as shown on figure 3103-2. Polarities shown arefor n-channel devices but the circuit may be used for p-channel types by reversing the polarities of the voltage and current 3103-2. Common-gate thermal impedance measurement circuit(gate-emitter on voltage method).The circuit consists of the DUT, two voltage sources, two current sources, and two electronic switches. During the heating phase of themeasurement, switches S1 and S2 are in position 1. The values of VCG and IE are adjusted to achieve the desired values of IC and VCE for the PH "heating" measure the initial and post heating pulse junction temperatures of the DUT, switches S1 and S2 are each switched to position puts the gate at the measurement voltage level VCG(M) and connects the current source IM to supply measurement current to theemitter. The values of VCG(M) and IM must be the same as used in the K factor calibration if actual junction temperature rise data isrequired. Figures 3103-4 and 3103-5 show the waveforms associated with the three segments of the Common-source thermal test circuit. A common-source configuration test circuit used to control the device and to measure thetemperature using the gate-emitter ON voltage as the temperature sensing parameter as shown on figure 3103-3. Polarities shown arefor n-channel devices but the circuit may be used for p-channel types by reversing the polarities of the voltage and current 31033MIL-STD-750DNOTE:The circuit consists of the DUT, four voltage sources, and two electronic switches. During the heating phase of themeasurement, switches S1 and S2 are in position 1. The values of VCE and VGE are adjusted to achieve the desired valuesof IC and VCE for the PH "heating" 3103-3. Common-source thermal impedance measurement circuit(gate-emitter on voltage method).METHOD 31034MIL-STD-750DTo measure the initial and post heating pulse junction temperatures of the DUT, switches S1 and S2 are each switched toposition 2. This puts the collector at the measurement voltage level VCE(M) and the gate at VGE(M), which must be adjustedto obtain IM. The values of VCE(M) and IM must be the same as used in the K factor calibration if actual junction temperaturerise data is required. Figures 3103-4 and 3103-5 show the waveforms associated with the three segments of the 3103-4. Device waveforms during the three segments of the thermal transient 31035MIL-STD-750DThe value of tMD is critical to the accuracy of the measurement and must be properly specified in order to ensuremeasurement repeatability. Note that some test equipment manufacturers include the sample and hold window time tSWwithin their tMD 3103-5. Second VGE measurement :The circuits for both common-gate and common-source thermal measurements can be modified so that VCE isapplied during both measurement and heating periods if the value of VCE is at least ten times the value of VGE(ON). Further, the common-gate circuit can be modified so that IM is continually applied as long as the IEcurrent source can be adjusted for the desired value of heating Source-drain forward voltage. Suitable sample-and-hold voltmeter or oscilloscope to measure source-drain forward voltage atspecified times. VGE(ON) shall be measured to within 5 mV, or within 5 percent of (VGE(ON)i - VGE(ON)f), whichever is Measurement of the TSP. The required calibration of VGE(ON) versus TJ is accomplished by monitoring VGE(ON) for therequired values of VCE and IM as the heat sink temperature (and thus the DUT temperature) is varied by external heating. Themagnitudes of VCE and IM shall be chosen so that VGE(ON) is a linearly decreasing function over the expected range of TJ during thepower pulse. For this condition, VCE must be at least three times VGE(ON). IM must be large enough to ensure that the device isturned on but not so large as to cause any significant self-heating. (This will normally be 1 mA for low power devices and up to 100 mAfor high power ones.) An example calibration curve is shown on figure K factor calibration. A calibration factor K (which is the reciprocal of VTC or the slope of the curve on figure 3103-4) can bedefined as:It has been found experimentally that the K-factor variation for all devices within a given device type class is small. The usual procedureis to perform a K factor calibration on a 10 to 12 piece sample from a device lot and determine the average K and standard deviation (VK).If VK is less than or equal to three percent of the average value of K, then the average value of K can be used for all devices within the VK is greater than three percent of the average value of K, then all the devices in the lot shall be calibrated and the individual values of Kshall be used in thermal impedance calculations or in correcting 'VGE(ON) values for comparison 3103-6. Example curve of VGE(ON) versus screening to ensure proper die attachment within a given lot, this calibration step is not required, ( , devices of a singlemanufacturer with identical PIN and case style). In such cases, the measure of thermal response may be 'VGE(ON) for a short heatingpulse, and the computation of 'TJ or Z4JX is not necessary. (For this purpose, tH shall be 10 ms for TO-39 size packages and 100 msfor TO-3 packages.)5. Calibration. K factor must be determined according to the procedure outlined in 4, except as noted in Reference point temperature. The reference point is usually chosen to be on the bottom of the transistor case directly below thesemiconductor chip in a TO-204 metal can or in close proximity to the chip in other styles of packages. Reference temperature pointlocation must be specified and its temperature shall be monitored using the thermocouple mentioned in during the preliminary it is ascertained that TX increases by more than five percent of measured junction temperature rise during the power pulse, then eitherthe heating power pulse magnitude must be decreased, the DUT must be mounted in a temperature controlled heat sink, or thecalculated value of thermal impedance must be corrected to take into account the thermal impedance of the reference point to the coolingmedium or heat 31037 MIL-STD-750DTemperature measurements for monitoring, controlling or correcting reference point temperature changes are not required if the tH valueis low enough to ensure that the heat generated within the DUT has not had time to propagate through the package. Typical values of tHfor this case are in the 10 ms to 500 ms range, depending on DUT package type and Thermal measurements. The following sequence of tests and measurements must be to the power pulse:(1)Establish reference point temperature TXi.(2)Apply measurement voltage VCE.(3)Apply measurement current IM.(4)Measure gate-emitter ON voltage VGE(ON)i (a measurement of the initial junction temperature). pulse parameters:(1)Apply collector-emitter heating voltage VH.(2)Apply collector heating current IH as required by adjustment of gate-emitter voltage.(3)Allow heating condition to exist for the required heating pulse duration tH.(4)Measure reference point temperature TXf at the end of heating pulse : TX measurements are not required if the tH value meets the requirements stated in power pulse measurements:(1)Apply measurement current IM.(2)Apply measurement voltage VGE.(3)Measure gate-emitter ON voltage VGE(ON)f (a measurement of the final junction temperature).(4)Time delay between the end of the power pulse and the completion of the VGE(ON)f measurement as defined by thewaveform of figure 3103-4 in terms of tMD plus value of thermal impedance, Z4JX, is calculated from the following formula:This value of thermal impedance will have to be corrected if TXf is greater than TXi by +5qC. The correction consists of subtracting thecomponent of thermal impedance due to the thermal impedance from the reference point (typically the device case) to the cooling mediumor heat sink. TX measurements are not required if the tH value meets the requirements stated in 31038 MIL-STD-750DThis thermal impedance component has a value calculated as follows:Where: HS = cooling medium or heat sink (if used).Then:Z4JX| = Z4JX| - Z4X-HS | | | | Corrected CalculatedNOTE: This last step is not necessary for die attach evaluation (see ).6. Test conditions and measurements to be specified and K factor Test conditions. Specify the following test current magnitude mA(See detail specification for current value) voltage magnitude V(See detail specification for voltage value) junction temperature C(Normally +25 C 5 C) junction temperature C(Normally +100 C 10 C) Data. Record the following VGE(ON) voltage VGE(ON) voltage K factor. Calculate K factor in accordance with the following For die attachment evaluation, this step may not be necessary (see ).METHOD 31039 Thermal impedance Test conditions. Specify the following test measuring current mA(Must be same as used for K factor calibration) measuring voltage V(Must be same as used for K factor calibration) heating current collector-emitter heating voltage heating time measurement time delay sample window time Ps(NOTE: IH and VH are usually chosen so that PH is approximately two-thirds of device rated power dissipation.) Data. Record the following initial reference temperature final reference temperature 'VGE(ON) data:'VGE(ON) VGE(ON) (ON)i initial source-drain voltage (ON)f final source-drain voltage VTX measurements are not required if the tH value meets the requirements stated in Thermal impedance. Calculate thermal impedance using the procedure and equations shown in 'VGE(ON) measurements for screening. These measurements are made for tH values that meet the intent of and therequirements stated in Test conditions. Specify the following test measuring current measuring voltage heating current collector-emitter heating voltage heating time sMETHOD measurement time delay sample window time Ps(The values of IH and VH are usually chosen equal to or greater than the values used for thermal impedance measurements.) Specified limits. The following data is compared to the specified 'VGE(ON) data:'VGE(ON) VGE(ON) (ON)i initial source-drain voltage (ON)f final source-drain voltage VCompute 'VGE(ON) 'TJ calculation. Optionally calculate 'TJ if the K factor results produce a V greater than three percent of the average value 310311/12 MIL-STD-750DMETHOD 3104THERMAL RESISTANCE MEASUREMENTS OF GaAs MOSFET's(CONSTANT CURRENT FORWARD-BIASED GATE VOLTAGE METHOD)1. Purpose. The purpose of this test method is to measure the thermal resistance of the MESFET under the specified conditions ofapplied voltage, current, and pulse width. The temperature sensitivity of the forward voltage drop of the gate-source diode is used as thejunction temperature indicator. This method is particularly suitable for completely packaged Definitions. The following symbols and terms shall apply for the purpose of this test :Measuring current in the gate-source :Heating current through the :Heating voltage between the drain and of the heating power pulse applied to DUT in watts; the product of IH and :Heating time during which PH is :Thermal calibration factor ( C/mV). :Junction temperature in degrees :Junction temperature in degrees Celsius before start of the power :Junction temperature in degrees Celsius at the end of the power :Reference temperature in degrees :Initial reference temperature in degrees :Final reference temperature in degrees :Forward-biased gate-source junction diode voltage drop in (i):Initial gate-source (f):Final gate-source :The time from the start of heating power (PH) removal to the completion of the final VGSf point thermal resistance in degrees Celsius/watt. 4JX for specified heating powerconditions is: :Comparison unit for screening devices against specification limits. Defined as the change in forward biasedgate-source voltage divided by heating current in Apparatus. The apparatus required for this test shall include the following as applicable to the specified test 31041 of Case reference point temperature. The case reference point temperature shall be measured using a thermocouple. Therecommended reference point should be located immediately outside the case under the heat source. Thermocouple material shall becopper-constantan (type T) or equivalent. The wire size shall be no larger than AWG size 30. The junction of the thermocouple shall bewelded to form a bead rather than soldered or twisted. The accuracy of the thermocouple and associated measuring system shall be Controlled temperature environment. A controlled temperature environment capable of maintaining the case temperature duringthe device calibration procedure to within 1 C over the temperature range of room temperature (approximately +23 C) to +100 K factor calibration setup. A K factor calibration setup, as shown on figure 3104-1, that measures VGSf for a specified value of IMin an environment that is both temperature controlled and measured. The current source must be capable of supplying IM with anaccuracy of 1 percent and have a compliance of at least 1 volt and not more than 2 volts. The voltage measurement of VGSf should bemade to 1 mV resolution. The device-to-current source wire size shall be sufficient to handle the measurement current (AWG size 26stranded is typically used for up to 10 mA).FIGURE 3104-1. K factor calibration Controlled temperature heat sink. Controlled temperature heat sink capable of maintaining the specified reference pointtemperature to within 5 of the preset (measured) Test circuit. The circuit used to control the device and to measure the temperature using the forward voltage of the gate-sourcediode as the temperature sensing parameter is shown on figure 3104-2. Polarities shown are for n-channel devices but the circuit may beused for p-channel types by reversing the polarities of the voltage and current 31042MIL-STD-750DNOTE:The circuit consists of the DUT, one voltage source, one current source, and one electronic switch. During the heatingphase of the measurement, switch S1 is in position 2. The value of VD is adjusted to achieve the desired values of ID andVDS for the PH "heating" 3104-2. Thermal resistance measurement circuit (constant current forward-biased gate voltage method).METHOD 31043MIL-STD-750DTo measure the initial and post heating pulse junction temperature of the DUT, switch S1 is switched to position 1. Thisdisconnects the VD source during the measurement time and allows for the measurement of VGSf(i) and VGSf(f) before and afterthe heating time, respectively. Figure 3104-3 shows the waveforms associated with the three segments of the 3104-3. Device waveforms during the three segments of the thermal resistance 31044MIL-STD-750DThe time required to make the second VGSf reading is critical to the accuracy of the measurement and must be properly specified inorder to ensure measurement repeatability. The definition of measurement delay time (tMD) are described by the waveform on 3104-4. Second VGSf measurement Source-drain forward voltage. Suitable sample-and-hold voltmeter or oscilloscope to measure source-drain forward voltage atspecified times. VGSf should be measured with 1 mV Measurement of the TSP VGSf. The required calibration of VGSf versus TJ is accomplished by monitoring VGSf for the requiredvalue of IM without any connection to the drain as the heat sink temperature (and thus the DUT temperature) is varied by external magnitude of IM should be chosen so that VGSf is a linearly decreasing function over the expected TJ range during the power must be large enough to ensure that the gate-source junction is turned on but not large enough to cause significant self-heating ordevice destruction. An example calibration curve is shown on figure 3104-5. Calibration calibration factor K (which is the reciprocal of the slope of the curve on figure 3104-5) can be defined as:It has been found experimentally that the K factor should vary less than several percent for all devices within a given device type usual procedure is to perform a K factor calibration on a 10 to 12 piece sample from a device lot and determine the average K andstandard deviation (V). If V is less than or equal to three percent of the average value of K, then the average value of K can be used for alldevices within the lot. If V is greater than the average value of K, then all the devices in the lot should be calibrated and the individualvalues of K should be used in thermal resistance Test Calibration. K factor must be determined according to the procedure outlined in Reference point temperature. The reference point is usually chosen to be on the bottom of the transistor case directly below thesemiconductor chip. Reference temperature point location must be specified and its temperature should be monitored using thethermocouple mentioned in during the preliminary testing. If it is ascertained that TXf increases by more than +5 C during the powerpulse, then either the heating power pulse magnitude must be decreased, the DUT must be mounted in a temperature controlled heatsink, or the calculated value of thermal resistance must be corrected to take into account the thermal resistance associated with thetemperature rise of the reference 31046 Thermal measurements. The following sequence of tests and measurements must be to the power pulse:(1)Establish reference point temperature: TXi.(2)Apply measurement current: IM.(3)Measure gate-source voltage drop: VGSf(i) (A measurement of the initial junction temperature). pulse parameters:(1)Maintain measurement current: IM.(2)Apply drain-source heating voltage: VH.(3)Measure drain heating current: IH.(4)Allow heating condition to exist for the required heating pulse width: tH.(5)Measure reference point temperature: TXf, at the end of heating pulse power pulse measurements:(1)Maintain measurement current: IM.(2)Measure gate-source voltage drop: VGSf(f) (A measurement of the final junction temperature).(3) Determine time delay between the end of the power pulse and the completion of the VGSf(f) measurement as defined bythe waveform of figure Thermal resistance. The value of thermal resistance, TJX, is calculated from the following formula:This value of thermal resistance will have to be corrected if TXf is greater than TXi. The correction consists of subtracting out thecomponent of thermal resistance due to the heat flow path from the reference point (typically the device case) to the heat sink and theenvironment. This thermal resistance component has a value calculated as follows:Then: TJX | = TJX | - TX-HS | | | | Corrected CalculatedMETHOD 31047 MIL-STD-750D An additional correction may be required because of the fast cooling of a typical MESFET heat source area. This requires that thethermal resistance measurements be made for two different values of tMD. Care must be taken to ensure that the shorter of the chosen tMD values does not lie within the non-thermal ( , electrical) switching transient region. Similarly, if the longer tMD value is too large, theresultant value of TJX will be too small for an accurate measurement due to device cooling. The correction for the calculated thermalresistance is given below for test conditions in which IM, VH, and tH remain the same for both tests. | | calculated value6. Test conditions and measurements to be specified and K factor the following test conditions:(1)IM current magnitude mA (See detail specification for current value.)(2)Initial junction temperature C (Normally +25 C 5 C.)(3)Final junction temperature C (Normally +100 C 10 C.) the following data:(1)Initial VGSf(i) voltage mV(2)Final VGSf(f) voltage K factor in accordance with the following die attachment evaluation, this step may not be necessary (see ). Thermal impedance Test conditions. Specify the following test measuring current mA (Must be same as used for K factor calibration) drain-source heating voltage heating time measurement time delay sample window time Ps(The value of VH is usually chosen to produce an IH value that results in a PH approximately two-thirds of the device rated powerdissipation.)METHOD 31048 Record data. Record the following initial reference temperature final reference temperature current during heating time 'VGSf data:'VGSf VGSf (i) initial gate-source voltage (f) final gate-source voltage TJX data:TJX C/WTX measurements are not required if the tH value meets the requirements stated in Thermal impedance calculations. Using the data collected in and the procedure and equations shown in , calculate thethermal 'VGSF measurements for screening. These measurements are made for tH values that meet the intent of and therequirements stated in Test conditions. Specify the following test measuring current drain-source heating voltage heating time measurement time delay sample window time Ps(The value of VH is usually chosen to produce an IH value that results in a PH equal to or greater than the values used for thermalimpedance measurements.) Specified limits. Data from one or more of the following is compared to the specified 'VGSf data:'VGSf VGSf (i) initial gate-source voltage (f) final gate-source voltage VCompute 'VSD mVMETHOD 'TJ data. Optionally calculate 'TJ if the K factor results (see 4. and ) produce a V greater than three percent of theaverage value of K and if the IH variation between devices to be compared is relatively : The test apparatus may be capable of directly providing a computed value of ' CU data. Optionally calculate CU for comparison purposes if the K factor results (see 4. and ) produce a V less than threepercent of the average value of K and if the IH variation between devices to be compared is relatively = comparison unitCU = 'VGSf/IH mV/ANOTE: The test apparatus may be capable of directly providing a computed value of 310410 MIL-STD-750DMETHOD METHOD FOR THERMAL RESISTANCEOF A BRIDGE RECTIFIER ASSEMBLY1. Purpose. This method describes a means to cause current to flow alternately through the legs of a single-phase or three-phasebridge assembly under condition to make it feasible determines its effective thermal resistance. The bridge is operated understeady-state IO conditions and the current in each leg is interrupted while readings are taken from which to calculate thermal Definitions. The following symbols and terminology shall apply for the purposes of this test :The forward-biased junction voltage of the DUT used for junction temperature sensing. For bridge, thisapplies to individual legs ( , one ac to one dc terminal). :The forward voltage at room temperature at Iref.` :The forward voltage at Iref and +100qC above that at :The computed forward voltage at Iref and at maximum rated :The initial VF value at Iref before the application of heating power, with the device at rated :The final VF value at Iref after stabilization of temperatures due to the application of rated current at ratedcase 'VF:The change in the TSP VF, due to the application of heating power to the DUT in :The maximum forward voltage resulting from the application of IO to the :The rated average current applied to the :The measurement current used to forward-bias the temperature sensing diode junction for measurementof :Voltage-temperature coefficient of VF with respect to TJ at a fixed value of Iref in :The DUT junction 'TJ:The change in TJ caused by the application of :The temperature-sensitive parameter (VF). :Step trace :Reference case temperature for measuring VN, when N = 1, 2, 3, or :Thermal resistance from device junction to a defined reference point ( , lead or ambient) in units :Thermal resistance from device junction to a defined reference point on the outside surface of the case inunits of of 6MIL-STD-750D3. Test circuit. The apparatus required for this test shall include the following, configured as shown on figures 3105-1 and source of 60 Hz, single or three phase sine wave (AC) capable of being adjusted to the desired value of IO and able tosupply the VFH value required by the DUT. The current source should be able to maintain the desired current to within r2percent during the entire time needed for temperature stabilization and constant-current source to supply IREF with sufficient compliance voltage range to turn on fully the junction of the diode legbeing fast recovery rectifier diodes with ratings exceeding IO, to provide isolation of the high-current source from IREFduring commutation of IO between voltage measurement circuit capable of accurately making the VF measurements within the available time interval (when theanti-parallel diodes are not conducting), with millivolt Procedure. Refer to figures 3105-1 and 3105-2, test circuits for single- and three-phase S1 open, and DUT at +20qC to +30qC (temperature T1), read VF1 of each leg at current IREF. Elevate the devicetemperature to +100qC above temperature T1 (temperature T2). Allow the device to stabilize until the junction temperature isat T2. Read VF2 of each leg at IREF current. Compute the TCVF of each leg as follows:TCVF = (VF1 - VF2) / +100qCCompute the expected VF2A at TJ = maximum rated as follows:VF2A = VF1 - [(TCVF) x (TJmax - T1)]Determine the average TCVF and the standard deviation of the TCVF from the readings on each leg. If the standard deviationis less than or equal to three percent of the average value of TCVF, TCVF may be used for all devices. If the standarddeviation is greater than three percent of the average value of TCVF, then the individual values of TCVF shall be used indetermining the performance of the the device held at T3, at or below rated case temperature of IO, close S1 and read VF3 for each closing S1, adjust the power source, the load resistor, or both to obtain the maximum rated IO (either IO1 or IO2,depending on the rated TC selected) and readjust the case temperature to the chosen rated value. Allow the device to achievestable junction temperatures (see note 1). VF4 (see figure 3105-2) for each leg at the same reference current (r1 percent) as in steps a. and b. (Theinstrumentation used to measure VF4 must have sufficient resolution to read it within 2 mV or 2 percent).NOTE: If VF3 for the leg is greater than VF2, TJ is less than VFH for each thermal resistance as follows:(1)Compute 'VF = VF4 - VF3 for each leg.(2)Compute 1/(3)Compute RTJC of the full bridge: Where: 'TJ is the average of all legs. VFH is the average of all legs and IO is the rectified output current of the full bridge. 2/ 3/ 4/5. Test condition to be specified. IO ____________________ TC ____________________ IREF ____________________ Frequency____________________ (if other than 60 Hz)6. Characteristics to be determined:Steady state thermal resistance. Unless otherwise specified, junction to care: 1/ If, under power, the case is held to T4, slightly above T3, a corrected 'TJ ('TJ(corr) = 'TJC - (T4 - T3)) should be used for step f(2). 2/ Step f(3) gives Rth for the bridge. The average per-leg Rth for a single-phase bridge is four times the value; six times for a three-phase bridge (see 3/). 3/ If desired, Rth of individual legs may be computed from the individual values of 'TJC and VFH. 4/ The power dissipated IO x 2VFH is a reasonable NOTES: voltage measurements shall be made using leads Kelvin-connected directly to the bridge terminals. is adjusted so that the VF4 step (tF4) shown on figure 3105-3 is 100 Ps r50 Ps and is clearly defined. A typical VAC might be 10 volts peak. Bridges with parasitic inductive components must adjust VAC so that after the inductive ringing settles, the VF4 step on figure 3105-3 (tF4) is 100 Ps r50 3105-1. Single phase NOTES: 1. All voltage measurements shall be made using leads Kelvin-connected directly to the bridge terminals. 2. VAC is adjusted so that the VF4 step (tF4) shown on figure 3105-3 is 100 Ps r50 Ps and is clearly defined. A typical VAC might be 10 volts peak. Bridges with parasitic inductive components must adjust VAC so that after the inductive ringing settles, the VF4 step on figure 3105-3 (tF4) is 100 Ps r50 3105-2. Three phase NOTE:VF4 "step trace" is provided when anti-paralleldiodes in circuit briefly commutate off (the accurrent passes through zero during each coolingcycle of individual bridge legs under ac testconditions.) NOTES: shown applies when IREF is positive. Thetrace in inverted when IREF is negative. is adjusted so that the VF4 step (tF4) shownon figure 3105-3 is 100 Ps r50 Ps and is clearlydefined. A typical VAC might be 10 volts with parasitic inductive components mustadjust VAC so that after the inductive ringingsettles, the VF4 step on figure 3105-3 (tF4) is 100Ps r50 3105-3. Oscilloscope 3126THERMAL RESISTANCE(COLLECTOR-CUTOFF-CURRENT METHOD)1. Purpose. The purpose of this test is to measure the thermal resistance of the device under the specified conditions. This methodis particularly applicable to the measurement of germanium devices having relatively large thermal response Test circuit. See figure 3126-1. Test circuit for thermal resistance (collector-cutoff-current method).3. Procedure. Switches S1 and S2 are ganged and are operated such that the time they are closed (heat interval) is much larger thanthe time they are open (measurement interval). S1 is arranged to open slightly before S2 opens, and the interval between the opening ofS1 and S2 is adjusted to be short compared to the thermal time constant of the device being measured. The length of the measurementinterval should be short compared to the thermal response time of the transistor being measured. When both switches are open, thevalue of ICBO is read as the drop across RB. If the ICBO varies during the measurement interval, the value immediately following theopening of S2 should be read. A calibrated oscilloscope makes a convenient detector. Care should be taken that the collector voltagestays Measurement interval. The measurement is made in the following manner: The case, ambient, or other reference point is elevatedto a high temperature T2, not exceeding the maximum junction temperature, and the cutoff current, ICBO, read with the constant-currentsource supplying no current. The reference temperature is then reduced to a lower temperature T1, and power, P1, is applied to heat thetransistor, by increasing the current from the constant current source, until the same value of ICBO is read as was read 31261 of 2 MIL-STD-750D4. Summary. The following conditions shall be specified in the detail temperature (see 3.). voltages or currents (see 3.).METHOD 31262MIL-STD-750DMETHOD IMPEDANCE MEASUREMENTS FOR BIPOLAR TRANSISTORS(DELTA BASE-EMITTER VOLTAGE METHOD)1. Purpose. The purpose of this test method is to measure the thermal impedance of the bipolar transistor under the specifiedconditions of applied voltage, current, and pulse duration. The temperature sensitivity of the base-emitter voltage is used as the junctiontemperature indicator. This test method is used to measure the thermal response of the junction to a heating pulse. Specifically, the testmay be used to measure dc thermal resistance, and to ensure proper die mountdown to its case. This is accomplished through theappropriate choice of pulse duration and heating power magnitude. The appropriate test conditions and limits are detailed in 6. Thismethod is also applicable for thermal testing of Darlington transistors. The measurement current (IM) must be large enough to ensurethat the Darlington output transistor is biased into the linear conduction mode of the temperature sensing measurement periods of thethermal Definitions. The following symbols and terms shall apply for the purpose of this test :Emitter current during measurement of the base-emitter voltage with applied collector-emitter :Heating current through the collector: (IC during heating). :Heating voltage between the collector and emitter: (VCE during heating). :Magnitude of the heating power pulse applied to DUT in watts; the product of IH and time during which PH is of VBE with respect to TJ; in mV/ :Thermal calibration factor equal to reciprocal of VTC; in :Junction temperature in degrees :Junction temperature in degrees Celsius before start of the power :Junction temperature in degrees Celsius at the end of the power TX:Reference temperature in degrees :Initial reference temperature in degrees :Final reference temperature in degrees :Base-emitter voltage drop in :Initial base-emitter voltage drop in :Final base-emitter voltage drop in :Measurement delay time is defined as the time from the removal of heating power PH to the start of the :Sample window time during which final VBE measurement is of 9MIL-STD-750Dm. ZTJX:Transient junction-to-reference point thermal impedance in degrees Celsius/watt. ZTJX for specified powerpulse duration is:Where: 'TX = change in reference point temperature during the heating pulse (see and For short heating pulses ( , die attach evaluation), this term is normally negligible.) :Equilibrium junction-to-reference point thermal resistance in degrees Apparatus. The apparatus required for this test shall include the following as applicable to the specified test thermocouple for measuring the case temperature at a specified reference point. The recommended reference point shallbe located on the case under the heat source. Thermocouple material shall be copper-constantan (type T) or equivalent. Thewire size shall be no larger than AWG size 30. The junction of the thermocouple shall be welded, rather than soldered ortwisted, to form a bead. The accuracy of the thermocouple and its associated measuring system shall be C. Propermounting of the thermocouple to ensure intimate contact to the reference point is critical for system controlled temperature environment capable of maintaining the case temperature during the device calibration procedure towithin C over the temperature range of +23 C to +100 C, the recommended temperatures for measuring K K factor calibration setup, as shown on figure 3131-1, measures VBE for specified values of IM and VCE (usually thesame as VH) in an environment in which temperature is both controlled and measured. The current source must be capableof supplying IM with an accuracy of 2 percent. The value of IM is usually chosen to be very small compared to IH so that thedevice junction and case temperatures are essentially the same. The voltage source must be capable of supplying VCE withan accuracy of 2 percent. The voltage measurement of VBE shall be made with a voltmeter capable of 1 mV resolution. Thedevice-to-current/voltage source wire size shall be sufficient to handle the measurement current (AWG size 22 stranded istypically used for up to 100 mA).FIGURE 3131-1. K factor calibration test circuit used to control the device and to measure the temperature using the base-emitter voltage as the temperaturesensing parameter as shown on figure 3131-2. Polarities shown are for NPN devices, but the circuit may be used for PNPtypes by reversing the polarities of the voltage and current 3131-2. Thermal impedance measurement-circuit (base-emitter method).The circuit consists of the DUT, a voltage source, two current sources, and an electronic switch. During the heating phase of themeasurement, switch SW is in position 2. The values of IE and VCB are adjusted to achieve the desired values of IC and VCB for the PH "heating" measure the initial and post heating pulse junction temperatures of the DUT, switch SW is switched to position 1. This applies thelow-valued emitter current IM to the device. IM is chosen not to cause significant self-heating relative to the heating current IH. If testingfor absolute magnitude values of thermal resistance or junction temperature change, the value of IM must be the same value used in theK factor calibration. Figures 3131-3 and 3131-4 show the waveforms associated with the three segments of the IE is adjusted to provide the desired IC for heating, the circuit of figure 3131-2 can be modified so that IM remains on at all timesand IE is switched in and out by is usually chosen to be 2 percent or less of the IC value. Typically, an IM value of 10 mA is sufficient for most bipolar transistors for IC up to 10 A. Darlington transistors having internal base resistors summing to 200 A or less typically require values of IM equal to 25 mAor 3131-3. Device waveforms during the three segments of the thermal transient value of tMD is critical to the accuracy of the measurement and must be properly specified in order to ensure measurementrepeatability. Note that some test equipment manufacturers include the sample and hold window time tSW within their tMD 3131-4. Example curve sample and hold 3131-5. Example curve of VGE(ON) versus sample-and-hold voltmeter or oscilloscope to measure base to emitter at specified times. VBE shall be measured towithin 5 mV, or within 5 percent of (VBEi - VBEf), whichever is Measurement of the TSP. The required calibration of VBE versus TJ is accomplished by monitoring VBE for the required values ofIM and VCE as the heat sink temperature (and thus the DUT temperature) is varied by external heating. The magnitudes of IM and VCEshall be chosen so that VBE is a linearly decreasing function over the expected range of TJ during the power pulse. IM must be largeenough to ensure that the base-emitter junction is turned on but not so large as to cause any significant self-heating. (This will normallybe 1 mA for small power devices and up to 100 mA for large ones. Darlington transistors with low-valued internal base resistors willtypically require greater than 20 mA in order to make sure the output transistor is turned on.) An example calibration curve is shown onfigure Die attachment screening. When screening to ensure proper die attachment within a given lot or in a group of the same typenumber devices of one manufacturer, this calibration step is not required. In such cases, the measure of thermal response may be 'VBEfor a short heating pulse, and the computation of 'TJ or ZTJX is not necessary. (For this purpose, tH shall be 10 ms for TO-39 sizepackages and 100 ms for TO-3 packages.)A calibration factor K (which is the reciprocal of VTC or the slope of the curve on figure 3131-4) can be defined as:It has been found experimentally that the K-factor variation for all devices within a given device type class is small. The usual procedureis to perform a K factor calibration on a 10 to 12 piece sample from a device lot and determine the average K and standard deviation (V).If VK is less than or equal to three percent of the average value of K, then the average value of K can be used for all devices within the VK is greater than three percent of the average value of K, then all the devices in the lot shall be calibrated and the individual values of Kshall be used in thermal impedance calculations or in correcting 'VBE values for comparison Test Calibration. K factor must be determined according to the procedure outlined in 4, except as noted in Reference point temperature. The reference point is usually chosen to be on the bottom of the transistor case directly below thesemiconductor chip in a TO-204 metal can or in close proximity to the chip in other styles of packages. Reference temperature pointlocation must be specified and its temperature shall be monitored using the thermocouple mentioned in during the preliminary it is ascertained that TX increases by more than five percent of measured junction temperature rise during the power pulse, then eitherthe heating power pulse magnitude must be decreased, the DUT must be mounted in a temperature controlled heat sink, or thecalculated value of thermal impedance must be corrected to take into account the thermal impedance of the reference point to the coolingmedium or heat measurements for monitoring, controlling, or correcting for reference point temperature changes are not required if the tHvalue is low enough to ensure that the heat generated within the DUT has not had time to propagate through the package. Typical valuesof tH for this case are in the 10 ms to 500 ms range, depending on DUT package types and Thermal resistance measurements. This is a thermal impedance measurement for the condition in which the heating time (tH)has been applied long enough to ensure that the temperature drop from the device junction to the case reference point in accordance has reached equilibrium and no longer increases for greater values of tH. In practical measurements, this condition can be assumedto exist when the rate of junction temperature change matches the rate of case temperature Prior to the power reference point temperature: measurement current: measurement voltage: base-emitter voltage: VBEi (a measurement of the initial junction temperature).METHOD Heating pulse collector-emitter heating voltage: Apply collector heating current: heating condition to exist for the required heating pulse duration: reference point temperature: TXf (at the end of heating pulse duration).(NOTE: TX measurements are not required if the tH value meets the requirements stated in ). Post power pulse measurement current measurement voltage base-emitter voltage VBEf (A measurement of the final junction temperature). delay between the end of the power pulse and the completion of the VBEf measurement as defined by the waveform offigure 3131-4 in terms of tMD + Value of thermal impedance. The value of thermal impedance, ZTJX, is calculated using the following formula:Under equilibrium conditions, the thermal resistance, TJX is calculated using the following formula: TJX = ZTJX | | equilibriumThis value of thermal impedance will have to be corrected if TXf is greater than TXi by +5 C. The correction consists of subtracting thecomponent of thermal impedance due to the thermal impedance from the reference point (typically the device case) to the cooling mediumor heat sink. TX measurements are not required if the tH value meets the requirements stated in thermal impedance component has a value calculated as follows:Where: HS = cooling medium or heat sink (if used).Then: ZTJX| = ZTJX| - ZTX-HS | | | | Corrected CalculatedNOTE: This last step is not necessary for die attach evaluation (see ).METHOD MIL-STD-750D6. Test conditions and measurements to be specified and K factor the following test conditions:(1)IM current magnitude mA(See detail specification for current value.)(2)VCE voltage magnitude V(Normally the same as VH.)(3)Initial junction temperature C(Normally +25 C 5 C.)(4)Final junction temperature C(Normally +100 C 10 C.) the following data:(1)Initial VBE voltage (VBE1) mV(2)Final VBE voltage (VBE2) K factor in accordance with the following die attachment evaluation, this step may not be necessary (see ). Thermal impedance Test conditions. Specify the following test measuring current mA(Must be same as used for K factor calibration.) collector-emitter voltage V(Must be same as used for K factor calibration.) collector heating current collector-emitter heating voltage heating time measurement time delay sample window time Ps(NOTE:IH and VH are usually chosen so that PH is approximately two-thirds of device rated power dissipation or greater.)METHOD recording. Record the following initial reference temperature final reference temperature 'VBE data:'VBE VBE initial base-emitter voltage final base-emitter voltage VTX measurements are not required if the tH value meets the requirements stated in Thermal impedance. Calculate thermal impedance using the procedure and equations shown in 'VBE measurements for screening. These measurements are made for tH values that meet the intent of and therequirements stated in Test conditions. Specify the following test measuring current measuring voltage collector heating current collector-emitter heating voltage heating time measurement time delay Psg. tSW sample window time Ps(The values of IH and VH are usually chosen equal to or greater than the values used for thermal impedance measurements.) Specified limits. The following data is compared to the specified 'VBE data:'VBE VBE initial base-emitter voltage final base-emitter voltage Optional calculation. Optionally calculate 'TJ if the K factor results (see 4. and ) produce a V greater than three percent ofthe average value of K.'TJ = K ('VBE) 3132THERMAL RESISTANCE(DC FORWARD VOLTAGE DROP, EMITTER BASE, CONTINUOUS METHOD)1. Purpose. The purpose of this test is to measure the thermal resistance of the device under the specified Test circuit. See figure 3132-1. Test circuit for thermal resistance (dc forward voltage drop, emitter base, continuous method).3. Procedure. The measurement technique assumes that the forward emitter voltage drop varies with temperature. It further assumesthat during the course of measurement, the variation in forward emitter voltage drop varies monotonically due to temperature and is muchgreater than that due to the variation with collector Measurement. The measurement is made in the following manner: The case, ambient, or other reference point is elevated to ahigh temperature T2, not exceeding the maximum junction temperature. Current IC is set to a value and a voltage applied to the collectorbase diode, V2. The value of V2 applied shall be low yet high enough so that the device is operating in a normal manner. V1EB is readunder these conditions. The reference temperature is reduced to a lower temperature T1 and VCC varied until the same value of V1EB isread as was read above. The thermal resistance is then Where: V1 is the collector voltage applied at temperature Summary. The following conditions shall be specified in the detail specification: temperatures. b. IC and 31321/2 MIL-STD-750DMETHOD 3136THERMAL RESISTANCE(FORWARD VOLTAGE DROP, COLLECTOR TO BASE, DIODE METHOD)1. Purpose. The purpose of this test is to measure the thermal resistance of the device under the specified conditions. This methodis particularly applicable to the measurement of germanium and silicon devices having relatively long thermal response Test circuit. See figure 3136-1. Test circuit for thermal resistance (forward voltage drop, collector to base, diode method).3. Procedure. Switches S1 and S2 are ganged switches and are so arranged that S2 opens very shortly after S1 opens and such thatthe delay between the openings is much shorter than the thermal response time of the device being measured. S1 and S2 should beclosed (heat interval) for a much larger time than they are open (measurement interval) and the measurement interval should be shortcompared to the thermal response time of the device being Measurement. The measurement is made in the following manner: The case, ambient, or other reference point is elevated to ahigh temperature T2, not exceeding the maximum junction temperature, and the collector-base voltage, VCB, is read. This reading ismade at the beginning of the measurement interval. An oscilloscope makes a convenient detector. The reference temperature is thenreduced to a lower temperature, T1. The heating power, P1, is adjusted by adjusting the heating current source in the emitter circuit untilthe same value of VCB is read as was read above. The value of 4 is calculated from the equation:Where: P1 = (n) (IC VCC + IE VEB)METHOD 31361 of 2 MIL-STD-750D4. Summary. The following conditions shall be specified in the detail specification:a. Test temperature (see ). voltages and currents (see 3.).METHOD 31362MIL-STD-750DMETHOD 3141THERMAL RESPONSE TIME1. Purpose. The purpose of this test is to measure the time required for the junction to reach 90 percent of the final value of junctiontemperature change following application of a step function of power dissipation under specified Apparatus. The apparatus used to determine the thermal response time shall be capable of demonstrating device conformance tothe minimum requirements of the individual Procedure. The thermal response time shall be determined by measuring the time required for the junction temperature (asindicated by a precalibrated temperature sensitive electrical parameter) to reach 90 percent of the final value of junction temperaturechange caused by a step function in power dissipation when the device case or ambient temperature, as specified, is held Summary. The device case or ambient temperature shall be specified in the detail 31411/2MIL-STD-750DMETHOD TIME CONSTANT1. Purpose. The purpose of this test is to measure the time required for the junction to reach percent of the final value of junctiontemperature change following application of a step function of power dissipation under specified Apparatus. The apparatus used to determine the thermal time constant shall be capable of demonstrating device conformance tothe minimum requirements of the individual Procedure. The thermal time constant shall be determined by measuring the time required for the junction temperature (asindicated by a precalibrated temperature sensitive electrical parameter) to reach percent of the final value of junction temperaturechange caused by a step function in power dissipation, when the device case or ambient temperature, as specified, is held Summary. The device case or ambient temperature shall be specified in the detail 3151THERMAL RESISTANCE, GENERAL1. Purpose. The purpose of this test is to measure the temperature rise per unit power dissipation of the designated junction abovethe case of the device or ambient temperature, under conditions of steady state Apparatus. The apparatus used to determine the thermal resistance shall be capable of demonstrating device conformance to theminimum requirements of the individual Procedure. The thermal resistance may be determined the junction power required to maintain the junction temperature constant (as indicated by a precalibratedtemperature sensitive electrical parameter) when the case of the device or ambient temperature, as specified, is changed by aknown the junction temperature (as indicated by a precalibrated temperature sensitive electrical parameter) when thejunction power is changed a known amount while the case of the device or ambient temperature, as specified, is Summary. The characteristic being measured, RTJC or RTJA shall be specified in the detail 31511/2MIL-STD-750DMETHOD 3161THERMAL IMPEDANCE MEASUREMENTS FOR VERTICAL POWER MOSFET's(DELTA SOURCE-DRAIN VOLTAGE METHOD)1. Purpose. The purpose of this test method is to measure the thermal impedance of the MOSFET under the specifiedconditions of applied voltage, current, and pulse duration. The temperature sensitivity of the forward voltage of the source-draindiode is used as the junction temperature indicator. This method is particularly suitable to enhancement mode, powerMOSFET's having relatively long thermal response times. This test method may be used to measure the thermal response ofthe junction to a heating pulse, to ensure proper die mountdown to its case, or the dc thermal resistance, by the proper choice ofthe pulse duration and magnitude of the heating pulse. The appropriate test conditions and limits are detailed in Definitions. The following symbols shall apply for the purpose of this test method:IM:Current in the source-drain diode during measurement of the source-drain :Heating current through the :Heating voltage between the drain and :Magnitude of the heating power pulse applied to DUT in watts; the product of IH and :Heating time during which PH is :Voltage-temperature coefficient of VSD with respect to TJ; in mV/ :Thermal calibration factor, equal to reciprocal of VTC; in :Junction temperature in degrees :Junction temperature in degrees Celsius before start of the power :Junction temperature in degrees Celsius at the end of the power :Reference temperature in degrees :Initial reference temperature in degrees :Final reference temperature in degrees :Source-drain diode voltage in :Initial source-drain voltage in :Final source-drain voltage in :Measurement delay time is defined as the time from the removal of heating power PH to the start of the VSD :Sample window time during which final VSD measurement is (M): Gate-source voltage applied during the initial and final measurement :Transient junction-to-reference point thermal impedance in degrees Celsius/watt. ZTJX for specified powerpulse duration is:Where: 'TX = Change in reference point temperature during the heating pulse (see and ). For short heating pulses, , die attach evaluation, this term is normally negligible.)METHOD 31611 of 9 MIL-STD-750D2. Apparatus. The apparatus required for this test shall include the following as applicable to the specified test thermocouple for measuring the case temperature at a specified reference point. The recommended reference pointshall be located on the case under the heat source. Thermocouple material shall be copper-constantan (type T) orequivalent. The wire size shall be no larger than AWG size 30. The junction of the thermocouple shall be welded toform a bead rather than soldered or twisted. The accuracy of the thermocouple and its associated measuring systemshall be C. Proper mounting of the thermocouple to ensure intimate contact to the reference point is critical forsystem controlled temperature environment capable of maintaining the case temperature during the device calibrationprocedure to within 1 C over the temperature range of +23 C to +100 C, the recommended temperatures formeasuring K K factor calibration setup, as shown on figure 3161-1, that measures VSD for a specified value of IM in anenvironment in which temperature is both controlled and measured. A temperature controlled, circulating fluid bathmay be used. The current source must be capable of supplying IM with an accuracy of 1 percent. The voltagesource must be capable of supplying a stable VGS(M) in the range of -1 to -5 V (opposite polarity for p-channeldevices). This voltage is applied in such a way as to turn the DUT off ( , gate negative with respect to source forn-channel device). The voltage measurement of VSD shall be made using kelvin contacts and with voltmeters capableof 1 mV resolution. The device-to-current source wire size shall be sufficient to handle the measurement current(AWG size 22 stranded is typically used for up to 100 mA).FIGURE 3161-1. K-factor calibration test circuit used to control the device and to measure the temperature using the forward voltage of the source-draindiode as the temperature sensing parameter as shown on figure 3161-2. Polarities shown are for n-channel devicesbut the circuit may be used for p-channel types by reversing the polarities of the voltage and current sample-and-hold voltmeter or oscilloscope to measure source-drain forward voltage at specified times. VSDshall be measured to within 5 mV, or within 5 percent of (VSDi - VSDf), whichever is 31612MIL-STD-750 circuit consists of the DUT, three voltage sources, a current source, and two electronic switches. During theheating phase of the measurement, switches S1 and S2 are in position 1. The values of VG and VD are adjusted toachieve the desired values of ID and VDS for the PH "heating" measure the initial and post heating pulse junction temperatures of the DUT, switches S1 and S2 are eachswitched to position 2. This puts the gate at the measurement voltage level VGS(M) and connects the currentsource IM to supply forward measurement current to the source-drain diode. The polarity of the current source issuch that the voltage applied to the MOSFET source and drain are opposite to those employed during normalMOSFET operation. Figures 3161-3 and 3161-4 show the waveforms associated with the three segments of 3161-2. Thermal impedance measurement circuit (source-drain diode method).METHOD 31613MIL-STD-750DFIGURE 3161-3. Device waveforms during the three segments of the thermal transient 3161-4. Second VSD measurement waveform. NOTE:The value of tMD is critical to the accuracy of the measurement and must be properly specified in order toensure measurement repeatability. Note that some test equipment manufacturers include the sample and holdwindow time tSW within their tMD 31614MIL-STD-750D3. Measurement of the TSP. The required calibration of VSD versus TJ is accomplished by monitoring VSD for the requiredvalue of IM as the heat sink temperature (and thus the DUT temperature) is varied by external heating. The magnitude of IMshall be chosen so that VSD is a linearly decreasing function over the expected range of TJ during the power pulse. IM must belarge enough to ensure that the source-drain junction is turned on but not so large as to cause any significant self-heating. (Thiswill normally be 10 mA for small power devices and up to 100 mA for large ones.) The VGS(M) value must be largeenough to decouple the gate from controlling the DUT; typical values are in the 1 to 5 V range. An example calibration curve isshown on figure Measurement of die attachment integrity. When screening to ensure proper die attachment integrity within a given lot or ina group of same type number devices of one manufacturer, this calibration step is not required. In such cases, the measure ofthermal response may be 'VSD for a short heating pulse, and the computation of 'TJ or ZTJX is not necessary. (For thispurpose, tH shall be 10 ms for TO-39 size packages and 100 ms for TO-3 packages.)FIGURE 3161-5. Example curve of VSD versus K factor calibration. A K factor calibration (which is the reciprocal of VTC or the slope of the curve on figure 3161-4) canbe defined as:It has been found experimentally that the K factor variation for all devices within a given device type class is small. The usualprocedure is to perform a K factor calibration on a 10 to 12 piece sample from a device lot and determine the average K andstandard deviation (V). If V is less than or equal to three percent of the average value of K, then the average value of K can beused for all devices within the lot. If V is greater than three percent of the average value of K, then all the devices in the lot shallbe calibrated and the individual values of K shall be used in thermal impedance calculations or in correcting 'VSD values forcomparison Test Calibration. K factor must be determined according to the procedure outlined in 3., except as noted in 31615 Reference point temperature. The reference point is usually chosen to be on the bottom of the transistor case directlybelow the semiconductor chip in a TO-204 metal can or in close proximity to the chip in other styles of packages. Referencetemperature point location must be specified and its temperature shall be monitored using the thermocouple mentioned in the preliminary testing. If it is ascertained that TX increases by more than +5 C of measured junction temperature riseduring the power pulse, then either the heating power pulse magnitude must be decreased, the DUT must be mounted in atemperature controlled heat sink, or the calculated value of thermal impedance must be corrected to take into account thethermal impedance of the reference point to the cooling medium or heat sink. Temperature measurements for monitoring,controlling, and correcting for reference point temperature changes are not required if the tH value is low enough to ensure thatthe heat generated within the DUT has not had time to propagate through the package. Typical values of tH for this case are inthe 10 ms to 500 ms range, depending on DUT package type and Thermal measurements. The following sequence of tests and measurements must be to the power pulse:(1)Establish reference point temperature (TXi).(2)Apply measurement current (IM).(3)Apply gate-source measurement voltage (VGS(M)).(4)Measure source-drain voltage drop (VSDi) (a measurement of the initial junction temperature). pulse parameters:(1)Apply drain-source heating voltage (VH).(2)Apply drain heating current (IH) as required by adjustment of gate-source voltage.(3)Allow heating condition to exist for the required heating pulse duration (tH).(4)Measure reference point temperature (TXf) at the end of heating pulse duration.(NOTE: TX measurements are not required if the tH value meets the requirements stated in ) power pulse measurements:(1)Apply measurement current (IM).(2)Apply gate-source measurement voltage (VGS(M)).(3)Measurement source-drain voltage drop (VSDf) (a measurement of the final junction temperature).(4)Time delay between the end of the power pulse and the completion of the VSDf measurement as defined by thewaveform of figure 3161-4 in terms of tMD + Thermal impedance. The value of thermal impedance (Z4JX) is calculated from the following formula:METHOD 31616 MIL-STD-750DThis value of thermal impedance will have to be corrected if TXf is greater than TXi by +5 C. The correction consists ofsubtracting out the component of thermal impedance due to the thermal impedance from the reference point (typically the devicecase) to the cooling medium or heat sink. TX measurements are not required if the tH value meets the requirements stated This thermal impedance component has a value calculated as follows: Where: HS = cooling medium or heat sink (if used). Then: ZTJX | = ZTJX | - ZTX-HS| | Corrected CalculatedNote: This last step is not necessary for die attach evaluation (see ).5. Test conditions and measurements to be specified and K factor Conditions data. Specify the following test current (IM) (see detail specification). voltage (VGS(M)) (in the range of 0 V to -6 V). junction temperature (TJ): +25 C 5 junction temperature (TJf): +100 C 10 Record data. Record the following VSD Final VSD Calculation data. Calculate K factor in accordance with the following Die attach procedure. K factor calibration (see ) may not be necessary for die attachment evaluation (see ). Thermal impedance Conditions data. Specify the following test conditions in the detail current (IM) (must be same as used for K factor calibration). heating current (IH). time (tH). heating voltage (VH).METHOD 31617 time delay (tMD). window time (tSW). voltage (VGS(M)) (must be same as used for K factor calibration). (NOTE: IH and VH are usually chosen so that PH is approximately two-thirds of device rated power dissipation). Record data. Record the following reference temperature (TXi). reference temperature (TXf). measurements are not required if the tH value meets the requirements stated in thermal impedance using the procedure and equations shown in 'VSD data. This parameter can either be read directly from suitable test instrumentation or calculated by taking thedifference between initial and final values of VSD ( , 'VSD = |VSD(i) - VSD(f)|.) Thermal resistance measurements. This is a thermal impedance measurement for the condition in which the heatingtime (tH) has been applied long enough to ensure that the temperature drop from the device junction to the case reference pointin accordance with has reached equilibrium and no longer increases for greater values of tH. In practical measurements,this condition can be assumed to exist when the rate of junction temperature change matches the rate of case Thermal response 'VDS measurements for screening. These measurements are made for tH values that meet the intentof and the requirements stated in Conditions data. Specify the following test conditions in the detail current (IM). heating current (IH). time (tH). heating voltage (VH). time delay (tMD). window time (tSW). voltage (VGS(M)) (must be the same as used if and when K factor calibration is performed ( )).(The values of IH and VH are usually chosen equal to or greater than the values used for thermal impedance measurements.)METHOD Specified limits. The following data is compared to the specified 'VSD as Optionally calculate 'TJ for comparison or screening purposes, or both, if the K factor results (see 3. and )produce a V greater than three percent of the average value of K. 'TJ = K ('VSD) in C6. Summary. The following conditions shall be specified in the detail Thermal measuring drain heating heating drain-source heating measurement time sample window Thermal response 'VSD measuring drain heating heating drain-source heating measurement time sample window 31619/10MIL-STD-750DMETHOD 3181THERMAL RESISTANCE FOR THYRISTORS1. Purpose. The purpose of this test is to measure the thermal resistance of thyristors under specified Test circuit. See figure 3181-1. Thermal resistance test Procedure. S1 is closed for a much longer interval (heat) than it is opened (measurement). The measurement interval should beshort compared to the thermal response time of the device being measured. The constant measurement current is a small current (of theorder of a few milliamperes) and so selected that the magnitude of VF1 changes appropriately with the device material (siliconapproximately 2 mV/ C) and junction temperature. The heating current source is Measurement. The measurement is made in the following manner. The case ambient or other reference point is elevated to ahigh temperature, T2, not exceeding the maximum junction temperature and the forward voltage drop VF1 read with the heating sourcesupplying no current ( , the forward voltage VF1 is to be read at the start of the measurement interval). An oscilloscope makes aconvenient detector. At T2 there will be a small power dissipated in the device due to the measurement current source. The reference isthen reduced to a lower temperature T1, and power P1 is applied to heat the device by increasing the current from the constant currentsource until the same value of VF1 is read as was read above. However, if P1 is calculated as the heating power contributed by theheating current source only the equation:Where: P1 = VF1 IF14. Summary. The following conditions shall be specified in the detail temperatures (see ). voltages and currents (see ).METHOD 31811/2 MIL-STD-750D3200 SeriesLow frequency testsUnless otherwise specified, the measurements shall be made at the electrical test frequency, 1,000 25 Hz. At 1,000 Hz, thereactive components may not be SHORT-CIRCUIT INPUT IMPEDANCE1. Purpose. The purpose of this test is to measure the input impedance of the device under the specified Test circuit. The circuit and procedure shown are for common emitter configuration. For other parameters the circuit andprocedure should be changed accordingly. NOTE: The biasing circuit shown is for purposes of illustration only. Other stable biasing circuits may be used (see ).FIGURE 3201-1. Test circuit for small-signal short-circuit input Procedure. The capacitors C1, C2, and C3 shall present short-circuits at the test frequency in order to effectively couple andbypass the test signal. The inductance L shall be resonated with a capacitor and the combination shall have a large impedancecompared with hie at the test frequency. RL shall be a short circuit compared with the output impedance of the device. Vg and Vbe aremeasured on high-impedance ac voltmeters after setting the specified values of IE and Summary. The following conditions shall be specified in the detail frequency (see 3.). voltages and currents (see 3.). to be SHORT-CIRCUIT FORWARD-CURRENT TRANSFER RATIO1. Purpose. The purpose of this test is to measure the forward-current transfer ratio of the device under the specified Test circuit. The circuit and procedure shown are for common emitter configuration. For other parameters the circuit andprocedure should be changed accordingly. NOTE: The biasing circuit shown is for purposes of illustration only. Other stable biasing circuits may be used (see ).FIGURE 3206-1. Test circuit for small-signal short-circuit forward-current transfer Procedure. The capacitors C1, C2, and C3 shall present short circuits at the test frequency in order to effectively couple andbypass the test signal. The inductance L shall be resonated with a capacitor and the combination shall have a large impedancecompared with hie at the test frequency. RL shall be a short circuit compared with the output impedance of the device. Vg, Vbe, and Vceshall be measured on high-impedance ac voltmeters after setting the specified values of IE and Summary. The following conditions shall be specified in the detail frequency (see 3.). voltage and currents (see 3.). to be 3216SMALL-SIGNAL OPEN-CIRCUIT OUTPUT ADMITTANCE1. Purpose. The purpose of this test is to measure the output admittance of the device under the specified Test circuit. The circuit and procedure shown are for common emitter configuration. For other parameters the circuit andprocedure should be changed accordingly. NOTE: The biasing circuit shown is for purposes of illustration only. Other stable biasing circuits may be used (see ).FIGURE 3216-1. Test circuit for small-signal open-circuit output Procedure. Inductance L1 shall be resonated with a capacitor and the combination shall have a large impedance compared with hieat the test frequency. The capacitors C1 and C2 shall present short circuits at the test frequency in order to effectively couple andbypass the test signal. Voltmeters Vbe and Vce shall be high impedance voltmeters. Then:4. Summary. The following conditions shall be specified in the detail voltages and currents (see 3.). frequency (see 3.). to be 32161/2MIL-STD-750DMETHOD 3221SMALL-SIGNAL SHORT-CIRCUIT INPUT ADMITTANCE1. Purpose. The purpose of this test is to measure the input admittance of the device under the specified Test circuit. The circuit and procedure shown are for common emitter. For other parameters the circuit and procedure should bechanged accordingly. NOTE: The biasing circuit shown is for purposes of illustration only. Other stable biasing circuits may be used (see ).FIGURE 3221-1. Test circuit for small-signal short-circuit input Procedure. The capacitors C1, C2, and C3 shall present short circuits at the test frequency in order to effectively couple andbypass the test signal. The inductance L shall be resonated with a capacitor and the combination shall have a large impedancecompared with hie at the test frequency. RL is optional and shall be a short circuit compared with the output impedance of the device. Vg and Vbe are measured on high-impedance ac Summary. The following conditions shall be specified in the detail frequency (see 3.).b. Test voltages and currents (see 3.). to be 32211/2MIL-STD-750DMETHOD 3231SMALL-SIGNAL SHORT-CIRCUIT OUTPUT ADMITTANCE1. Purpose. The purpose of this test is to measure the output admittance of the device under the specified Test circuit. The circuit and procedure shown are for common emitter configuration. For other parameters the circuit andprocedure should be changed 3231-1. Test circuit for small-signal short-circuit output Procedure. The capacitors C1 and C2 shall present short circuits at the test frequency in order to effectively couple and bypass thetest signal. Resistor RC is not zero but chosen for any convenient Summary. The following conditions shall be specified in the detail frequency (see 3.). voltages or to be 32311/2MIL-STD-750DMETHOD 3236OPEN CIRCUIT OUTPUT CAPACITANCE1. Purpose. This test is designed to measure the open circuit output capacitance of the device under the specified Test circuit. The circuit and procedure shown are for common base configuration. For other parameters the circuit and procedureshould be changed 3236-1. Test circuit for open circuit output Procedure. The bridge should have low dc resistance between its output terminals and should be capable of carrying the specifiedcollector current without affecting the desired accuracy of measurement. The emitter should be open-circuited to ac and the frequency ofmeasurement shall be as specified. Capacitor C should be sufficiently large to provide a short circuit at the test Measurement. The capacitance reading instrument is nulled with the circuitry connected, thereby eliminating errors due to thestray capacitances of the circuit wiring. The device to be measured is inserted into the test socket, is properly biased, and the outputcapacitance is Summary. The following conditions shall be specified in the detail voltages or currents (see 3.). frequency (see 3.). to be 32361/2MIL-STD-750DMETHOD CAPACITANCE(OUTPUT OPEN-CIRCUITED OR SHORT-CIRCUITED)1. Purpose. The purpose of this test is to measure the shunt capacitance of the input terminals of the device under the Test circuit. See figure 3240-1. NOTE: For other configurations, the circuit may be modified in such a manner that it is capable of demonstrating device conformance to the minimum requirements of the individual 3240-1. Test circuit for input capacitance (output open-circuited or short-circuited).3. Procedure. The bridge should have a low dc resistance between the input terminals and should be capable of carrying the requiredemitter current without effecting the desired accuracy of measurement. The specified voltages or voltage and current shall be applied tothe terminals; an ac small signal shall be applied to the input terminals. Switch SW shall be opened or closed depending upon whetherthe output is intended to be ac open-circuited or ac short-circuited. The input capacitance shall then be measured. The capacitancereading instrument is nulled with the circuitry connected, thereby eliminating errors due to stray capacitances and circuit Summary. The following conditions shall be specified in the detail voltages or currents (see 3.). frequency (see 3.). output is to be open-circuited or 3241DIRECT INTERTERMINAL CAPACITANCE1. Purpose. The purpose of this test is to measure the direct interterminal capacitance between specified terminals using specifiedelectrical Apparatus. A direct capacitance bridge or resonance method may be used to determine the value of the direct Procedure. The direct interterminal capacitance can be determined by using method A or method Method A. The specified voltage shall be applied between specified terminals: an ac small signal shall be applied to the terminalsand the direct interterminal capacitance shall be measured. The lead capacitance beyond .5 inch ( mm) from the body seat shall beeffectively eliminated by suitable means such as test socket shielding. The abbreviations and symbols used are defined as follows: Ccb(dir): Collector to base interterminal direct capacitance. Ceb(dir): Emitter to base interterminal direct capacitance. Cce(dir): Collector to emitter interterminal direct Method B. A suitable resonance method can be utilized to measure the following two-terminal capacitances: C1: Capacitance between collector terminal and ground, with base and emitter terminals grounded. C2: Capacitance between the base terminal and ground, with collector and emitter terminals grounded. C3: Capacitance between the collector and base terminals strapped together and ground, with the emitter terminal direct interterminal capacitance can then be calculated from the following relationship:The direct interterminal capacitance for other configurations can be determined by suitable modifications of the above procedure. Suchmodifications shall be capable of demonstrating device conformance to the minimum requirements of the individual Summary. The following conditions shall be specified in the detail biasing voltage or 32411/2MIL-STD-750DMETHOD FIGURE1. Purpose. The purpose of this test is to measure the noise figure of the device under the specified Apparatus. An average responding rms calibrated indicator shall be used in addition to other suitable apparatus to measure thenoise figure of the Procedure. The voltage and current specified in the individual specification shall be applied to the terminals, and the noise figureshall then be measured at the frequency specified in the individual specification (normally 1,000 Hz) with an input resistance of 1,000 Aand as referred to a 1 Hz Summary. The following conditions shall be specified in the detail voltage or RESPONSE1. Purpose. The purpose of this test is to measure the pulse response (td, tr, ts, and tf) of the device under the specified Test circuit. See figures 3251-1 and 3251-1. Test circuit FIGURE 3251-2. Test circuit for pulse for pulse response, test response, test condition B. condition Procedure. The pulse response of the device shall be measured using test condition A or Test condition A. The device shall be operated in the common emitter configuration as shown on figure 3251-1 with the collectorload resistance (RC) and collector supply voltage (VCC) specified. When measuring delay or rise time, IB(0) and IB(1) or VBE(1) shallbe specified. When measuring storage or fall time, IB(1) or VBE(1) and IB(2) or VBE(2) shall be specified. The input transition and thecollector voltage response detector shall have rise and response fall times such that doubling these responses will not affect the resultsgreater than the precision of measurement. The current and voltages specified shall be constant. Stray capacitance of the circuit shallbe sufficiently small so that doubling it does not affect the test results greater than the precision of measurement. IB(0) = prior off state base current. VBE(0) = prior off state base to emitter voltage. IB(1) = on state base current. VBE(1) = on state base to emitter voltage. IB(2) = post off state base current. VBE(2) = post off state base to emitter of Test condition B. The device shall be operated in the test circuit shown on figure 3251-2 (constant current drive) with the voltagesand component values as specified. The pulse or square-wave generator and scope shall have rise and fall response times such thatdoubling these responses will not affect the results greater than the precision of Summary. The following conditions shall be specified in the detail condition (A or B). load resistance (RC) and collector supply voltage (VCC) for resistance (RB) collector load resistance (RC), and collector supply voltage (VCC) for voltages or currents (see 3.).METHOD 3255LARGE SIGNAL POWER GAIN1. Purpose. The purpose of this test is to measure the ratio of ac output power to the ac input power (usually specified in dB) underspecified large signal Test circuit. The test circuit shall be as specified in the detail Procedure. The procedure shall be as specified in the detail Summary. The following conditions shall be specified in the detail voltages and frequency (if other than 1,000 Hz). 32551/2MIL-STD-750DMETHOD 3256SMALL SIGNAL POWER GAIN1. Purpose. The purpose of this test is to measure the ratio of the ac output power to the ac input power under the specifiedconditions (usually specified in dB) for small signal power Test circuit. See figure 3256-1. NOTE: For other configurations, the circuit should be modified in such a manner that the circuit is capable of demonstrating device conformance to the individual 3256-1. Test circuit for small-signal power Procedure. The specified voltage(s) and current(s) should be applied to the terminals; an ac small signal should be applied to theinput terminals of the specified circuit. The resistors R1 and R2 should have values larger than the hie of the device. The phase angle 1between the input current and Vbe shall be considered to be 0, if the specified test frequency is less than the extrapolated unity gainfrequency (ft) of the , for common emitter:METHOD 32561 of 2 MIL-STD-750DFor other configurations, modifications to the procedure should be made in such a manner that it is capable of demonstrating deviceconformance to the individual Summary. The following conditions shall be specified in the detail specification:a. Test voltage(s) and current(s). frequency (if other than 1,000 Hz).METHOD 32562 MIL-STD-750DMETHOD UNITY GAIN FREQUENCY1. Purpose. The purpose of this test is to determine the extrapolated unity gain frequency (gain band width product) of the deviceunder the specified Test circuit. The test circuit employed in determining the extrapolated unity gain frequency shall be that which is used formeasuring the magnitude of the common emitter small-signal short-circuit current transfer ratio. (See method 3306.)3. Procedure. The magnitude of the common emitter short-circuit current transfer ratio shall be determined at the specified frequencywith the specified bias voltages and currents applied. The product of the specified signal frequency (f) and the measured commonemitter small-signal short-circuit current transfer ratio (hfe) is the extrapolated unity gain frequency (ft).4. Summary. The following conditions shall be specified in the detail current and 3266REAL PART OF SMALL-SIGNAL SHORT-CIRCUIT INPUT IMPEDANCE1. Purpose. The purpose of this test is to measure the resistive component of the small signal short-circuit input impedance of thedevice under the specified Test circuit. See figure :The circuit shown is used for measuring the common emitter real part ofthe small-signal short-circuit input impedance. For other deviceconfigurations, the above circuitry should be modified in such a mannerthat it is capable of demonstrating device conformance to the minimumrequirements of the individual 3166-1. Test circuit for real part of small-signal short-circuit input Procedure. The voltage and current specified shall be applied to the terminals. An ac small signal of the frequency specified shallbe applied to the input terminals and the output terminals shall be ac short-circuited. The real part of the input impedance shall then Summary. The following conditions shall be specified in the detail specification:a. Test voltage and 32661/2MIL-STD-750D3300 SeriesHigh frequency testsCare shall be taken that, in designing the circuit and transistor mounting, adequate shielding and decoupling are provided andthat series inductances in circuits are 3301SMALL-SIGNAL SHORT-CIRCUIT FORWARD-CURRENT TRANSFER-RATIOCUTOFF FREQUENCY1. Purpose. The purpose of this test is to measure the forward-current transfer-ratio cutoff frequency under the specified Test circuit. The circuit and procedure shown are for common base configuration. For other parameters the circuit and procedureshould be changed accordingly. NOTE: Normal VHF circuit precautions should be taken. At frequencies higher than 10 MHz, the use of this circuit may lead to excessive errors. The biasing circuit shown is for the purposes of illustration only and any stable biasing circuit may be 3301-1. Test circuit for small-signal short-circuit forward-current transfer-ratio cutoff Procedure. The voltages and currents shall be as specified. Resistors RG and RE shall be large to present open circuits to RC shall be small to present a short circuit to hob. Capacitors C1, C2, C3, and C4 shall present short circuits at the testfrequency to effectively couple and bypass the test circuitry shall be frequency independent. This can be checked by removing the device from the circuit and shortingbetween emitter and collector with no bias voltages applied. Care should be taken to ensure that the generator has asufficiently pure waveform and that the high-impedance voltmeter is adequately sensitive to enable the measurement to bemade at a low enough signal level to avoid the introduction of harmonics by the generator is set to a frequency at least 30 times lower than the lowest cutoff frequency limit and the low frequency hfb ismeasured. The frequency is then increased until the magnitude of hfb has fallen to 1/ 2 of its low frequency value. This isthe cutoff 33011 of 2MIL-STD-750D4. Summary. The following conditions shall be specified in the detail voltages and currents (see 3.). to be 33012MIL-STD-750DMETHOD SHORT-CIRCUIT FORWARD-CURRENT TRANSFER RATIO1. Purpose. The purpose of this test is to measure the forward-current transfer ratio under the specified Test circuit. The circuit (see figure 3306-1) and procedure shown are for common emitter configuration. For other parameters thecircuit and procedure should be changed accordingly. NOTE: The biasing circuit shown is for purpose of illustration only. Other stable biasing circuits may be used (see ).FIGURE 3306-1. Test circuit for small-signal short-circuit forward-current transfer Procedure. Capacitors C1, C2, and C3 shall present short circuits in order to effectively couple and bypass the test signal at thefrequency of measurement. The value of RB shall be sufficiently large to provide a constant current source. Resistor RC shall be a shortcircuit compared to the output impedance of the device. With the device removed from the circuit, a shorting link is placed between thebase and collector and the output voltage of the signal generator is adjusted until a reading of one (in arbitrary units) is obtained on thehigh-impedance ac voltmeter, VCE. With the device in the circuit and biased as specified, the reading on voltmeter VCE is now equal tothe magnitude of (hfe). (NOTE: Care must be taken to assure that the output signal is not clipped.)4. Summary. The following conditions shall be specified in the detail frequency (see 3.). voltages and currents (see ). to be 3311MAXIMUM FREQUENCY OF OSCILLATION1. Purpose. The purpose of this test is to measure the maximum frequency of oscillation for the device under the specified Test circuit. The circuit utilized for the maximum frequency of oscillation test shall be as specified in the detail Procedure. The voltage(s) and current(s) specified shall be applied to the device in the circuit specified, and the circuit resonantfrequency shall be increased until oscillation ceases. The frequency at which oscillation ceases is the maximum frequency of Summary. The following conditions shall be specified in the detail voltage(s) and current(s).METHOD 33111/2MIL-STD-750DMETHOD 3320RF POWER OUTPUT, RF POWER GAIN, AND COLLECTOR EFFICIENCYTEST CONDITION A1. Purpose. The purpose of this test is to measure the RF power output, RF power gain, and collector efficiency of a transistor underactual operating conditions in a specific RF amplifier test circuit. Test condition A shall be valid for devices operating at RF power levelsgreater than 10 dBm when tested in the frequency range between 10 MHz and 2 Apparatus. All referenced equipment may be replaced by equivalents suitable for the frequency of test. The equipment set up shallbe as shown on figures 3320-1 and Procedure. The test fixture shall be disconnected and directional couplers number 1 and number 2 shall be directly connectedusing a minimum number of connectors. The RF switch shall be set to the output position 'C' and the frequency and RF power sourceadjusted to the specific conditions by monitoring the frequency counter and RF power meter respectively. The RF switch shall be set toposition 'A' and the variable attenuator adjusted to obtain the identical reading as power out in position 'C'. The test fixture shall bereconnected with the DUT inserted and the dc power supply adjusted to the specified voltage. The circuit output tuning shall be adjustedfor maximum power gain and circuit input tuning for minimum reflected power. (The RF switch shall be alternated between power in,reflected power, and power out while tuning and this procedure shall be repeated as many times as necessary to obtain minimumreflected power and maximum power out.) The power in level shall be checked before taking the final measurement. If input reflectedpower calibration is required, the above procedure shall be repeated with directional coupler number 1 reversed and switch position 'A'changed to switch position 'B'.NOTE:Minimum reflected power is defined as minimum reading obtained with switch in position 'B' and maintaining power Power output. Power output (Pout) is measured by adjusting the RF power source to obtain the specified forward input powerand reading the output power in Power input. Power input (Pin) is measured by adjusting the RF power source to obtain the specified forward output power andreading the input power in Power gain. Power gain (Gp) is measured by adjusting the RF power source to the value of Pin which produces the specified Pout. Pin and Pout shall be observed and the gain (in dB) determined as Collector efficiency. Collector efficiency (O) is measured by adjusting the RF source to the specified Pin (or Pout) and reading Pout. The collector efficiency shall be computed as follows: Where: IC = collector current VCC = collector supply voltageMETHOD 33201 of 10 MIL-STD-750DFIGURE 3320-1. Test equipment 3320-2. Alternate test equipment fixture is the circuit as described in the applicable detail specification (circuit layout and components quality are critical). power source shall be a unit capable of generating desired power level at desired frequency with a harmonic and spuriouscontent t 20 dB below operating frequency level of 100 MHz to 1 RF isolator shall be a device ( , pad, circulator) capable of establishing t 20 dB of isolation between RF power source andtest fixture. (A resistive attenuator shall be used for out-of-band isolation.)METHOD 33202MIL-STD-750DFIGURE 3320-2. Alternate test equipment set-up - attenuators (or fixed, if calibrated): Attenuators are set so that the actual power into and out of test fixture are on directional coupler number 2 shall be calibrated against a known working standard either by means of a calibrationchart or suitable adjustment if variable. Attenuation at position 'A' of directional coupler number 1 shall be calibrated or adjustedso that actual power at test fixture is known. Attenuation at position 'B' shall be adjusted to establish sensitivity needed tomeasure Reflected power (normally 10 dB less than the attenuation at position 'A'). switch may be eliminated if additional power meters are than one directional coupler may be used in place of coupler number 1. If more than one coupler is used, the Power In andReflected power position may be directional couplers shall have a minimum directivity of 30 dB and a nominal 20 dB coupling attenuation except where testlevel sensitivities require 10 dB or less dc power supply shall be RF decoupled at the test readings shall be sensed at test fixture, not at power supply. number 2 and 50 : load may be replaced by coaxial fixed attenuators (Narda) and a power meter (HP 432A). Powermeter may be separate or connected to the one shown on the other side through port C of the RF switch (see figure 3320-2). harmonic or subharmonic contents less than 20 dB down from the desired signal are present and could influence the measuredoutput power, a suitable filter (low pass, band pass, or high pass) shall be employed between the attenuator(s) and power meterused for output power Summary. The following conditions shall be specified in the detail voltage (and current, if applicable).b. Test input (or output). circuit with critical parts and layout to be CONDITION B1. Purpose. The purpose of this test is to measure the RF power output, RF power gain, and collector efficiency of a transistor underactual operating conditions in a specific RF amplifier test circuit. Test condition B shall be valid for devices operating at RF power levelsgreater than 0 dBm when tested in the frequency range between 100 MHz and 10 Apparatus. All referenced equipment may be replaced by equipment of equal or superior capability. A typical equipment setup is asfollows (see figure 3320-3). All components shall be suitable for the frequency range of 33203MIL-STD-750DFIGURE 3320-3. RF test 33204MIL-STD-750DFIGURE 3320-4. Alternate output 33205MIL-STD-750D NOTE: The unswitched port automatically terminates the alternate coupler port in 50 : when using the coax switch specified in the equipment 3320-5. Alternate input 33206MIL-STD-750DNOTES: 1. The test fixture referred to in this document is the circuit which is described in the applicable detailed specification (circuit layoutand component quality are critical). 2. The RF power source shall be a unit capable of generating desired power levels at the frequency of interest. All harmonics andspurious content shall be at least 26 dB below the output level. When necessary, a suitable filter (low pass or band pass) shouldbe used between the RF source and the isolator to reduce the second harmonic. A similar filter should be used in the outputcircuit between the coupler and the power meter unless the harmonic levels of the DUT are less than 26 dB below themeasurement level. If the filter is to be used, its insertion loss should be calibrated and accounted for at the measurementfrequency. 3. Coupler number 2 and the 50 : load may be replaced by a coaxial fixed attenuator and a power meter (see figure 3320-4). Ifemployed, the output low pass filter should be placed between the attenuator and power meter. 4. The two power meters connected to coupler number 1 may be replaced by one power meter and a good quality coaxial transferswitch. (The use of such switches is discouraged at frequencies above 4 GHz unless precautions are taken to account for RFlosses (see figure 3320-5).) These switches are designed for use in 50 systems. The unswitched port is automaticallyterminated internally with 50 : and loads the alternate coupler port. 5. The RF isolator shall be a device ( , pad, circulator) capable of establishing t 20 dB of isolation between RF power source andtest fixture. 6. The directional couplers shall have a minimum directivity of 30 dB and a nominal 20 dB coupling attenuation except where testlevel sensitivities require 10 dB or less attenuation. (Greater accuracy results from using the highest coupling possible,consistent with the measurement.) 7. The dc power supply shall be RF decoupled at the test fixture. 8. Voltmeter readings shall be sensed at the test fixture, not at power supply. 9. A calibrated wavemeter may be used in lieu of the frequency counter specified on figure Equipment list. (All referenced equipment may be replaced by equipment of equal or superior quality.)Equipment Manufacturer ModelCW sourceAs desired 1/IsolatorAddington Labs 1/Dual directional couplerNARDA3022*Variable attenuatorMerrimacAu-25A5Average power meterHewlett-Packard432 ACoax switchHewlett-Packard33311 B/CFixed filterMicrolab FXR 1/Power supplyHewlett-Packard6296 ARF test fixture(See individual specification)VoltmeterMeter-mod Instruments420 RAmmeterMeter-mod Instruments420 R2. Test RF setup calibration the RF test setup as on figure 3320-3 and with the test fixture removed, hook up the output of coupler number 1 to theinput of coupler number 2 (attenuation of directional coupler number 2 shall be calibrated against a known working standardeither by means of calibration chart or suitable adjustment if variable). the frequency of the source as indicated by the readout of the frequency counter or a dip in the power level when using anin-line the variable attenuator on the source by decreasing the attenuator until the desired power level is observed on the outputpower meter (apply correction factor if necessary to correct for coupler number 2 or output attenuator error). the input power meter, and adjust the attenuator associated with this meter until it reads the same power output as theoutput power meter in (If using the alternate input setup on figure 3320-5, calibrate with coaxial switch in the forwardposition.) the output coupler and power meter from the circuit so that the output of coupler number 1 is open the attenuator associated with the reflected power meter until it reads the same as the forward meter. With a calibratedshort on the input of the coupler observe the difference in reflected power between an open circuit condition and a the reflected power variable attenuator for an average between the open and short circuit readings. (If using thealternate input setup on figure 3320-5, the reflected power port is automatically calibrated when the forward power is calibratedif both ports of the coupler are balanced.)______1/ Model depends on frequency of test: See manufacturer's catalog for correct model the input attenuator until power output is zero (calibration completed). multiple frequency testing is required repeat through for each frequency, noting the variable attenuator and powersource settings for each specified frequency. All equipment must be returned to the noted settings during test at eachspecified frequency RF certain the dc power supply is With the RF test setup on figure 3320-3 or with alternate circuits of figures 3320-4 and 3320-5, and with the test fixture inplace, clamp a device in the test on the dc power supply. Precautions should be observed to prevent voltages exceeding the specified test the attenuator at the source until the input power reads the appropriate the output power, reflected power, and collector current (record, if necessary). the attenuator at the source until the input power reads through as required with the previously noted power source and attenuator settings if other test frequenciesare off the dc power the device from the test Data required (measurements). output (Pout) is measured by adjusting the RF power source as outlined in to obtain the specified forward inputpower and reading the output power in input (Pin) is measured by adjusting the RF power source to obtain the specified forward output power and reading theinput power in gain (Gp) is calculated from the measured RF data. Pin and Pout shall be observed and the gain (in dB) determined efficiency (K) is calculated from the measured RF and dc data. The collector efficiency shall be computed as follows: Where: IC = Collector current VCC = Collector supply power may be observed directly from the power meter if the setup is calibrated as specified in Even thoughreflected power may not be part of the RF specifications, it is included here because it is an indication as to how much of theinput is actually reaching the device. Good practice dictates that, where possible, the external circuit should be adjusted fromminimum reflected 33209 MIL-STD-750D4. Summary. The following conditions shall be specified in the detail specification:a. Test voltage (and current if applicable). input or power circuit with critical parts and layout (s) to be (s) to be test 332010MIL-STD-750D3400 SeriesElectrical characteristics tests for MOS field-effect transistorsCircuits are shown for n-channel field-effect transistors in one circuit configuration only. They may readily be adapted forp-channel devices and for other circuit VOLTAGE, GATE TO SOURCE1. Purpose. The purpose of this test is to determine if the breakdown voltage of the field-effect transistor or IGBT under the specifiedconditions is greater than the specified minimum limit. For the IGBT, replace the drain and source MOSFET designations with collectorand emitter IGBT designations, D = C and S = Test circuit. See figure 3401-1. NOTE: The ammeter shall present essentially a short circuit to the terminals between which the current is being measured or the voltmeter readings shall be corrected for the drop across the 3401-1. Test circuit for breakdown voltage, gate to Procedure. The resistor R1 is a current-limiting resistor and should be of sufficiently high resistance to avoid excessive currentflowing through the device and current meter. The voltage shall be gradually increased, with the specified bias condition (condition A, B,C, or D) applied, from zero until either the minimum limit for V(BR)GSX 1/ or the specified test current is reached. The device isacceptable if the minimum limit for V(BR)GSX is reached before the test current reaches the specified value. If the specified test currentis reached first, the device shall be considered a Summary. The following conditions shall be specified in the detail current (see 3.). condition:A: Drain to source: Reverse bias (specify bias voltage).B: Drain to source: Resistance return (specify resistance of R2).C: Drain to source: Short : Drain to source: Open V(BR)GSX: Breakdown voltage, gate to source, with the specified bias condition applied from drain to TO SOURCE VOLTAGE OR CURRENT1. Purpose. The purpose of this test is to measure the gate to source voltage or current of the field-effect transistor or IGBT under thespecified conditions. For the IGBT, replace the drain and source MOSFET designations with collector and emitter IGBT designations, D= C and S = Test circuit. See figure 3403-1. NOTE: The ammeter shall present essentially a short circuit to the terminals between which the current is being measured or the voltmeter readings shall be corrected for the drop across the 3403-1. Test circuit for breakdown voltage, gate to Procedure. The voltage source and bias source shall be adjusted to bring VDS and ID to their specified values. The voltage VGS or current IG may then be Summary. The following conditions shall be specified in the detail voltages and currents (see 3.). to be 3404MOSFET THRESHOLD VOLTAGE1. Purpose. This method establishes the means for measuring MOSFET threshold voltage. This method applies to bothenhancement-mode and depletion-mode MOSFETs, and for both silicon on sapphire and bulk-silicon MOSFETs. It is for use primarily inevaluating the response of MOSFETs to ionizing radiation, and for this reason the test differs from conventional methods for measuringthreshold threshold voltage, VGS(TH): The gate-to-source voltage at which the drain current is reduced to the leakage current, asdetermined by this Apparatus. The apparatus shall consist of a suitable ammeter, voltmeters, and voltage sources. The apparatus may be manuallyadjusted or, alternatively, may be digitally programmed or controlled by a computer. Such alternative arrangements shall be capable ofthe same accuracy as specified below for manually adjusted Ammeter (A ). The ammeter shall be capable of measuring current in the range specified with a full scale accuracy 1of percent or Voltmeters (V and V . The voltmeters shall have an input impedance of 10 m: or greater and have a capability of 1 2measuring 0 to 20 V with a full scale accuracy of percent or Voltage sources (V and V ). The voltage sources shall be adjustable over a nominal range of 0 V to 20 V, have GS DSa capability of supplying output currents at least equal to the maximum rated drain current of the device to be tested, and have noise andripple outputs less than percent of the output :The absolute maximum values of power dissipation, drain-to-source voltage, drain current, or gate-to-source voltagespecified is either the applicable acquisition document or the manufacturer's specifications shall not be exceededunder any N-channel Test circuit for n-channel devices. The test circuit shown on figure 3404-1 shall be assembled and the apparatus turned the voltage sources VDS and VGS set to 0 volts, the MOSFET to be tested shall be inserted into the test circuit. Thegate-to-source polarity switch shall be set to the appropriate position, and voltage source VGS shall be set V negative with respect tothe anticipated value of threshold voltage VGS(TH). Voltage source VDS shall be adjusted until voltmeter V2 indicates the specifieddrain-to-source voltage VDS. The current ID, indicated by ammeter A1, and the gate-to-source voltage VGS, indicated by voltmeter V1,shall be measured and Measurement for n-channel devices. The measurement shall be repeated at gate-to-source voltages which are volts more positive until either the maximum gate-to-source voltage or maximum drain current is reached. If the gate-to-sourcevoltage reaches 0 volts before either of these limits has been reached, the gate-to source polarity switch shall be changed as necessaryand measurements shall continue to be made at gate-to-source voltages which are successively volts more positive until one ofthese limits has been P-channel Test circuit for p-channel devices. The test circuit shown on figure 3404-2 shall be assembled and the apparatus turned the voltage sources VGS and VDS set to 0 volts, the MOSFET to be tested shall be inserted into the test circuit. Thegate-to-source polarity switch shall be set to the appropriate position, and voltage source VGS shall be set V positive with respect tothe anticipated value of threshold voltage VGS(TH). Voltage source VDS shall be adjusted until voltmeter V2 indicates the specifieddrain-to-source voltage VDS. The current ID, indicated by ammeter A1, and thegate-to-source voltage VGS, indicated by voltmeter V1, shall be measured and 34041 of Measurement for p-channel devices. The measurement shall be repeated at gate-to-source voltages are successively voltsmore negative until either the maximum gate-to-source voltage or maximum drain current is reached. If the gate-to-source voltagereaches 0 volts before either of these limits has been reached, the gate-to-source polarity switch shall be changed as necessary andmeasurements shall continue to be made at gate-to-source voltages which are successfully volts more negative until one of theselimits has been Leakage current measurement. Using method 3415, the leakage current shall be Drain-to-source voltage. The drain-to-source voltage shall be as specified in Gate-to-source voltage. The gate-to-source voltage shall be five volts different from the anticipated threshold voltage in thedirection of reduced drain Gate-to-source voltage graph. The gate-to-source voltage, VGS shall be plotted versus the square-root of thedrain current minus the leakage current, ID - IL. At the point of maximum slope, a straight line shall be extrapolated downward. Thethreshold voltage VGS(TH) is the intersection of this line with the gate-to-source voltage axis. Examples are shown on figure Report. As a minimum, the report shall include the device identification, the test date, the test operator, the test temperature, thedrain-to-source voltage, the range of gate-to-source voltage, the leakage current, and the threshold Summary. The following conditions shall be specified in the detail temperature. Unless otherwise specified, the test shall be performed at drain of gate-to-source 34042MIL-STD-750D NOTE: Gate-to-source polarity switch set at: A for enhancement mode B for depletion modeFIGURE 3404-1. Test circuit for n-channel 34043MIL-STD-750DNOTE: Gate-to-source polarity switch set at:A for enhancement modeB for depletion modeFIGURE 3404-2. Test circuit for p-channel 34044MIL-STD-750DFIGURE 3404-3. Examples of 34045/6MIL-STD-750DMETHOD TO SOURCE ON-STATE VOLTAGE1. Purpose. The purpose of this test is to measure the drain to source voltage of the field-effect transistor or IGBT at the specifiedvalue of drain current. For the IGBT, replace the drain and source MOSFET designations with collector and emitter IGBT designations,D = C and S = Test circuit. See figure 3405-1. Test circuit for drain to source on-state Procedure. The specified bias condition shall be applied between the gate and source and the voltage source shall be adjusted tobring ID to the specified value. The voltage VDS may then be Summary. The following conditions shall be specified in the detail current (see 3.). to source bias condition:A: Voltage-biased (specify bias voltage and polarity).B: VOLTAGE, DRAIN TO SOURCE1. Purpose. The purpose of this test is to determine if the breakdown voltage of the field-effect transistor or IGBT under the specifiedconditions is greater than the specified minimum limit. For the IGBT, replace the drain and source MOSFET designations with collectorand emitter IGBT designations, D = C and S = Test circuit. See figure 3407-1. NOTE: The ammeter shall present essentially a short circuit to the terminals between which the current is being measured or the voltmeter readings shall be corrected for the drop across the 3407-1. Test circuit for breakdown voltage, drain to Procedure. The resistor R1 is a current-limiting resistor and should be of sufficiently high resistance to avoid excessive currentflowing through the device and current meter. The voltage shall be gradually increased from zero, with the specified bias condition(condition A, B, C, or D) applied, until either the minimum limit for V(BR)DSX 1/ or the specified test current is reached. The device isacceptable if the minimum limit for V(BR)DSX is reached before the test current reaches the specified value. If the specified test currentis reached first, the device shall be considered a Summary. The following conditions shall be specified in the detail current (see 3.). condition:A: Gate to source: Reverse bias. (Specify bias voltage.)B: Gate to source: Resistance return. (Specify resistance of R2.)C: Gate to source: Short : Gate to source: Open V(BR)DSX: Breakdown voltage, drain to source, with the specified bias condition applied from gate to REVERSE CURRENT1. Purpose. The purpose of this test is to measure the gate reverse current of the field-effect transistor or IGBT under the specifiedconditions. For the IGBT, replace the drain and source MOSFET designations with collector and emitter IGBT designations, D = C andS = Test circuit. See figure 3411-1. NOTE: The ammeter shall present essentially a short-circuit to the terminals between which the current is being measured or the volt meter readings shall be corrected for the drop across the 3411-1. Test circuit for gate reverse Procedure. The specified dc voltage shall be applied between the gate and the source with the specified bias condition (condition A,B, C, or D) applied to the drain. The measurement of current shall be made at the specified ambient or case Summary. The following conditions shall be specified in the detail voltage (see 3.). temperature if other than +25 C 3 C ambient (see 3.). condition:A: Drain to source: Reverse bias. (Specify bias voltage.)B: Drain to source: Resistance return. (Specify resistance of R2.)C: Drain to source: Short : Drain to source: Open CURRENT1. Purpose. The purpose of this test is to measure the drain current of the field-effect transistor or IGBT under the specifiedconditions. For the IGBT, replace the drain and source MOSFET designations with collector and emitter IGBT designations, D = C andS = Test circuit. See figure 3413-1. NOTE: The ammeter shall present essentially a short-circuit to the terminals between which the current is being measured or the volt meter readings shall be corrected for the drop across the 3413-1. Test circuit for drain Procedure. The specified voltage shall be applied between the drain and source with the specified bias condition (condition A, B, C,or D) applied to the gate. The measurement of current shall be made at the specified ambient or case Summary. The following conditions shall be specified in the detail voltage (see 3.). temperature if other than +25 C 3 C ambient (see 3.). to be condition:A: Gate to source: Reverse bias. (Specify bias voltage.)B: Gate to source: Forward bias. (Specify bias voltage.)C: Gate to source: Short : Gate to source: Open REVERSE CURRENT1. Purpose. The purpose of this test is to measure the drain reverse current of the field-effect transistor or IGBT under the specifiedconditions. For the IGBT, replace the drain and source MOSFET designations with collector and emitter IGBT designations, D = C andS = Test circuit. See figure 3415-1. NOTE: The ammeter shall present essentially a short-circuit to the terminals between which the current is being measured or the volt meter readings shall be corrected for the drop across the 3415-1. Test circuit for drain reverse Procedure. The specified dc voltage shall be applied between the drain and the gate. The measurement of current shall be made atthe specified ambient or case Summary. The following conditions shall be specified in the detail voltage (see 3.). temperature if other than +25 C 3 C ambient (see 3.).METHOD DRAIN TO SOURCE ON-STATE RESISTANCE1. Purpose. The purpose of this test is to measure the resistance between the drain and source of the field-effect transistor or IGBTunder the specified static condition. For the IGBT, replace the drain and source MOSFET designations with collector and emitter IGBTdesignations, D = C and S = Test circuit. See figure 3421-1. Test circuit for static drain to source on-state Procedure. The specified bias condition shall be applied between the gate and source and the voltage source shall be adjusted sothat the specified current is achieved. The drain to source voltage shall then be Summary. The following conditions shall be specified in the detail to source bias condition:A: Voltage-biased (specify bias voltage and polarity).B: Short 3423SMALL-SIGNAL, DRAIN TO SOURCE ON-STATE RESISTANCE1. Purpose. The purpose of this test is to measure the resistance between the drain and source of the field-effect transistor under thespecified small-signal Test circuit. See figure 3423-1. NOTE: The ac voltmeter shall have an input impedance high enough that halving it does not change the measured value within the required accuracy of the 3423-1. Test circuit for small-signal, drain to source on-state Procedure. The specified bias condition shall be applied between the gate and the source and an ac sinusoidal signal current, Id, ofthe specified rms value shall be Summary. The following conditions shall be specified in the detail current (see 3.). to source bias condition:A: Voltage-biased (specify bias voltage and polarity).B: 34231/2MIL-STD-750DMETHOD 3431SMALL-SIGNAL, COMMON-SOURCE, SHORT-CIRCUIT, INPUT CAPACITANCE1. Purpose. The purpose of this test is to measure the input capacitance of the field-effect transistor under the specified Test circuit. The circuit and procedure shown are for common-source configuration. For other configurations the circuit andprocedure should be changed 3431-1. Test circuit for small-signal, common-source, short-circuit, input Procedure. The capacitors C1 and C2 shall present short circuits at the test frequency. L1 and L2 shall present a high acimpedance at the test frequency for isolation. The bridge shall have low dc resistance between its output terminals and should becapable of carrying the test current without affecting the desired accuracy of Summary. The following conditions shall be specified in the detail voltages and to be 34311/2MIL-STD-750DMETHOD 3433SMALL-SIGNAL, COMMON-SOURCE, SHORT-CIRCUIT, REVERSE-TRANSFER CAPACITANCE1. Purpose. The purpose of this test is to measure the reverse-transfer capacitance of the field-effect transistor under the Test circuit. The circuit and procedure shown are for common-source configuration. For other configurations the circuit andprocedure should be changed accordingly. Terminal 2 of bridge shall be the terminal with an ac potential closest to the ac potential of theguard terminal so as to provide an effective short circuit of the input. NOTE: The dotted connection between the case and ground shall be used for devices in which the case is not internally electrically connected to any element. If the case is internally electrically connected to any element, the dotted connection shall not be 3433-1. Test circuit for small signal, common-source, short-circuit, reverse-transfer Procedure. The capacitor C1 shall present a short circuit at the test frequency. L1 and L2 shall present a high ac impedance atthe test frequency for isolation. The bridge shall have low dc resistance between its output terminals and should be capable ofcarrying the test current without affecting the desired accuracy of Summary. The following conditions shall be specified in the detail voltages and to be 34331/2MIL-STD-750DMETHOD 3453SMALL-SIGNAL, COMMON-SOURCE, SHORT-CIRCUIT, OUTPUT ADMITTANCE1. Purpose. The purpose of this test is to measure the output admittance of the field-effect transistor under the specified Test circuit. The circuit and procedure are shown for common-source configuration. For other configurations the circuit andprocedure should be changed 3453-1. Test circuit for small-signal, common-source, short-circuit, output Procedure. The capacitors C1, C2, and C3 shall present short circuits at the test frequency in order to effectively couple andbypass the test signal. R1 and RL shall be short circuits compared with the output impedance of the device. After setting the specifieddc conditions, the VDS meter shall be disconnected from the circuit while measuring e1 and e2. The voltages e1 and e2 shall bemeasured with high-impedance ac Summary. The following conditions shall be specified in the detail voltages and to be 34531/2MIL-STD-750DMETHOD 3455SMALL-SIGNAL, COMMON-SOURCE, SHORT-CIRCUIT, FORWARD TRANSADMITTANCE1. Purpose. The purpose of the test is to measure the forward transadmittance of the field-effect transistor under the specifiedsmall-signal Test circuit. The circuit and procedure shown are for common-source configuration. For other configurations the circuit andprocedure should be changed 3455-1. Test circuit for small-signal, common-source, short-circuit, forward Procedure. The capacitors C1, C2, C3, and C4 shall present short circuits at the test frequency in order to effectively couple andbypass the test signal. R1 shall be a short circuit compared with the input impedance of the device. RL shall be a short circuit comparedwith the output impedance of the device. The voltages e1 and e2 shall be measured with high-impedance ac Summary. The following conditions shall be specified in the detail voltages and to be 34551/2 MIL-STD-750DMETHOD 3457SMALL-SIGNAL, COMMON-SOURCE, SHORT-CIRCUIT,REVERSE TRANSFER ADMITTANCE1. Purpose. The purpose of the test is to measure the reverse transfer admittance under the specified small-signal Test circuit. The circuit and procedure shown are for common-source configuration. For other configurations, the circuit andprocedure should be changed 3457-1. Test circuit for small-signal, common-source, short-circuit, reverse transfer Procedure. The capacitors C1, C2, C3, and C4 shall present short circuits at the test frequency in order to effectively couple andbypass the test signal. R1 shall be impedance matched to the generator. RL shall be a short-circuit compared with the input impedanceof the device. The rms voltages e1 and e2 shall be measured with high-impedance ac shall be adjusted to the specified value, then the gate voltage supply shall be adjusted so that VGS or ID equals the specified value,and the voltages e1 and e2 shall be Summary. The following conditions should be specified in the detail voltages and to be 34571/2MIL-STD-750DMETHOD 3459PULSE RESPONSE (FET)1. Purpose. The purpose of this test is to measure the pulse response (td(on), tr, td(off), and tf) of the field-effect transistor under thespecified Test circuit. The test circuit shall be as shown in the individual Procedure. The FET shall be tested in the specified circuit. Vin(on), Vin(off), pulse generator impedance, all circuit components,and supply voltages shall be as 3459-1. Pulse characteristics are defined on figure 3459-1. The rise time, fall time, duty cycle or pulse repetition rate, and pulse width of theinput waveform together with the input resistance, capacitance, and response time of the response detector shall all be such thathalving or doubling these parameters will not affect the results of the measurement greater than the precision of Summary. The following conditions shall be specified in the detail pulse levels Vin(on) and Vin(off). impedance of pulse with all supply to be 34591/2MIL-STD-750DMETHOD 3461SMALL-SIGNAL, COMMON-SOURCE, SHORT-CIRCUIT, INPUT ADMITTANCE1. Purpose. The purpose of this test is to measure the input admittance of the field-effect transistor under the specified Test circuit. The circuit and procedure shown are for common-source configuration. For other configurations the circuit andprocedure should be changed 3461-1. Test circuit for small-signal, common-source, short-circuit, input Procedure. The capacitors C1, C2, C3, and C4 shall present short circuits at the test frequency in order to effectively couple andbypass the test signal. R1 facilitates the adjustment of e1. Its use is optional. R2 shall be such that dc biasing is possible. RL shall bea short circuit compared with the input impedance of the device. VDS shall be adjusted to the specified value, then the gate voltagesupply shall be adjusted so that VGS or ID equals the specified value, and the voltages e1 and e2 shall be Summary. The following conditions shall be specified in the detail voltages and to be 34611/2MIL-STD-750DMETHOD 3469REPETITIVE UNCLAMPED INDUCTIVE SWITCHING1. Purpose. This purpose of this test method is to determine the repetitive inductive avalanche switching capability of power Scope. This method is intended as an endurance test for any power switching device designed and specified with repetitiveavalanche Circuitry. The basic circuit is shown on figure 3469-1. The circuit shall be designed so that all stray reactances are held to aminimum. The inductor L shall be of a fast response Definitions. The following terms and symbols apply to this test method:TJ:Junction (max):The maximum specified junction :Thermal resistance from the junction to the :Load inductance in accordance with :Repetitive avalanche energy, :Repetitive avalanche current, :On state :Case :Power dissipation of (BR):Breakdown or avalanche voltage of :Power supply :Stray circuit :time in Screening. The DUT must be screened prior to avalanche and meet all specified Calculations. The energy delivered to the DUT can be calculated as follows:a.[]METHOD 34691 of 2MIL-STD-750Db. NOTE: RS z Energy delivered. The actual energy delivered to the DUT can vary depending on the real value of RS. Since this is test circuitdependent, the actual energy delivered must be verified by observing the voltage across the DUT and current through the DUTwaveforms (see figure 3469-1). Empirically record the V(BR), IAR, and tav. Then calculate:EAR = 1/2 V(BR)IAR tav (in accordance with figure 3469-1).If this empirically derived value is not greater than or equal to the specified minimum EAR value, the circuit must be compensated until Junction temperature. TJ during the test must be held constant to TJ (max) +0 C -10 C, based on the case temperature of theDUT and the RTJC or the junction temperature as determined using a TSP. The power dissipated in the DUT is equal to the sum of theon energy and the avalanche energy multiplied by the frequency. The Eon in most cases can be : PD = f * (EAR + Eon) TJ = PD * RTJC + TCThe case temperature of the DUT will be measured at a specified reference point under the heat source. It is also possible to measurethe temperature of the heat sink at a specified reference point provided that an accurate value of the thermal resistancecase-to-heat-sink-reference-po int is known. The measured junction temperature based on measurements of a TSP may also besubstituted for the junction temperature calculated from case Number of pulses. The DUT will be avalanched for a specified minimum number of pulses at specified conditions. Uponcompletion the specified device parameters will be Summary. Unless otherwise specified in the detail specifications, the following parameters shall be as follows:EAR:(Repetitive avalanche energy (joules)).IAR:(Repetitive avalanche current (amperes)).TJ:+150 C +0 C, -10 :2 Ps minimum, 2 Ps :500 Hz, x 108 minimum number of pulses. Supply voltage 50 Failure criteria. The DUT must be within all specified parameter limits at the completion of the test. As a minimum, VBR shall begreater than or equal to rated breakdown voltage and applicable leakage 34692 MIL-STD-750DMETHOD PULSE UNCLAMPED INDUCTIVE SWITCHING1. Purpose. This method is applicable to power MOSFET's and IGBT. For the IGBT, replace the drain and source MOSFETdesignations with collector and emitter IGBT designations, D = C and S = E. The purpose of this test method is to screen out weakdevices which otherwise may result in costly equipment failures. This is accomplished by providing a controlled means of testing thecapability of a power MOSFET or IGBT to withstand avalanche breakdown while turning off with an unclamped inductive load underspecified conditions. The device capability is a strong function of the peak drain current at turn-off and the circuit inductance. Since novoltage clamping circuits or devices are employed, essentially, all of the energy stored in the inductor must be dissipated in the DUT atturn-off. It is not the intent of this test method to closely duplicate actual application conditions where device temperatures may approachmaximum rated value, repetition rates may be 10 to 100 kHz, and voltage transients are usually only a few microseconds in , experience has shown that failures in actual applications can be greatly reduced or eliminated if devices are tested foravalanche operation under defined circuit conditions at very low repetition rates and at room ambient Test procedures. The specified value of inductance L shall be connected into the circuit (see figures 3470-1 and 3470-2). Thegate pulse shall be applied to the device at the specified repetition rate. The VDD supply voltage shall be applied. The gate pulse widthshall be adjusted as necessary until the specified drain current ID is reached. Test failures are defined as those devices which 3470-1. Unclamped inductive switching circuit. NOTE: The test circuit, shown for n-channel devices, is also applicable for p-channel devices with appropriate changes in polarities and of 3MIL-STD-750D NOTES:The following notes are provided in the interest of achieving comparable results from various test circuits employed to performthis core inductors are recommended for this test to avoid the possibility of core problems. If iron coreinductors are used, care must be taken such that core saturation is not changing the effective value tothe inductance L which will lead to non-repeatable test resistance of the inductor must be controlled since I2R losses in the inductor will decrease thepercentage of LI2/2 stored energy transferred to the DUT. The relationship R = (VDS/ID) appliesfor one percent of the stored energy being dissipated in the resistance. For two percent loss, R = 2(.015) (VDS/ID) or (VCE/IC). The resistance loss shall be limited to two percent maximum, if notcompensated by the gate to source resistor shall be closely connected to the test device. The gate to source resistorshall be a low enough value that the switching performance of the device does not affect the test and theinductor in the drain circuit determines the current waveform. The design of the pulsed gate sourcemust be such that RGS or RGE is the effective gate to source resistance during the tf portion of the repetition rate and duty cycle of the test shall be chosen so that device average junction temperaturerise is minimal. Limits of one pulse per second or percent duty cycle are recommended. The devicepeak junction temperature shall not exceed maximum rated the VDD or VCE power supply remains in series with the inductor during the tf interval then the energytransferred to the DUT may be considerably higher than LI2/2. If the gate pulse width is adjusted so thatVCC or VDD < VDS or VCE then the contribution of the power supply will be less than 10 percent ofthe stored LI2/2 3470-2. Unclamped inductive switching power Summary. The following conditions shall be specified in the detail peak current (ID). gate voltage (VGS). otherwise specified, gate to source resistor (RGS) = 25 : to 50 :. case temperature (TC). (L). 3471GATE CHARGE1. Purpose. The purpose of this test is to measure the gate charge (Qg) of power MOSFET's and IGBT. For the IGBT, replace thedrain and source MOSFET designations with collector and emitter IGBT designations, D = C and S = Test 1: Qg(th) is the gate charge that must be supplied to reach the minimum specified gate-sourcethreshold voltage. It establishes line loci through the origin of a Q = f(Vgs) graph that is invariant withID, VDD, and TJ. It establishes a relationship with capacitance ( ,b. Test 2: Qg(on) is the gate charge that must be supplied to reach the gate-source voltage specified for the devicerDS(on) Test 3: Qgm(on) is the gate charge that must be supplied to the device to reach the maximum rated gate-sourcevoltage. Qgm(on) and Qg(on) establish line loci on a Q = f(Vgs) graph that may be considered invariant with IDand TJ. The slope of the loci is invariant with VDD, while the intercept with the Q axis is variant with Test 4: VGP is the gate voltage necessary to support a specified drain current. VGP, ID is a point on the devicegate voltage, drain current transfer characteristic. VGP is variant with IDand TJ. It may be measured one of twoways:(1) Using a dc parameter test set employing a circuit similar to that described in method 3474 for SOA settingVDD >> VGS.(2)Using a gate charge test circuit employing a constant ID drain Test 5: Qgs is the charge required by CGS to reach a specified ID. It is variant with ID and TJ. It is measured ina gate charge test circuit employing a constant drain current Test 6: Qgd is the charge supplied to the drain from the gate to change the drain voltage under constant draincurrent conditions. It is variant with VDD and may be considered invariant with ID and TJ. It can be related to aneffective gate-drain capacitance ( , Crss = Qgd/VDD). The effective input capacitance is: Ciss = CGS + Test The gate charge test is performed by driving the device gate with a constant current and measuring the resultinggate source voltage response. Constant gate current scales the gate source voltage, a function of time, to afunction of coulombs. The value of gate current is chosen so that the device on-state is of the order of 100 resulting gate-source voltage waveform is nonlinear and is representative of device behavior in the low tomid-frequency ranges. The slope of the generated response reflects the active device capacitance(Cg = dQg/dVGS) as it varies during the switching transition. The input characteristic obtained from this testreflects the chip design while avoiding high frequency Figure 3471-1 is the test circuit schematic for testing an n-channel device. Polarities are simply reversed for ap-channel Figure 3471-2 is an example of a practical embodiment of figure 3471-1. It illustrates a gate drive and instrumentcircuit that will test n- and p-channel 34711 of 9MIL-STD-750Dd. The circuit has Ig programmability ranging from microamperes to milliamperes. For very large power MOSFETdevices, the output Ig can be extended to tens of milliamperes by paralleling additional CA3280 The circuit provides an independent gate voltage clamp control to prevent voltage excursions from exceeding testdevice gate voltage CA3240E follower ensures that the smallest power devices will not be loaded by the oscilloscope.(Rin = T :, IIN = 10 pA, CIN = 4 pF). charge is to be measured starting at zero gate voltage to a specified gate voltage The magnitude of input step constant gate current Ig should be such that gate propagation and inductive effectsare not evident. Typically this means the device on-state should be of the order of 100 The dynamic response, source impedance, and duty factor of the pulsed gate current generator are to be suchthat they do not materially affect the , the instrument used for a gate charge measurement is an oscilloscope with an input amplifier and probe. Theswitching response and probe impedance are to be such that they do not materially affect the measurement. Too low a proberesistance relative to the magnitude of Ig can significantly increase the apparent Qg for a given VGS. Too high a value ofprobe capacitance relative to the device Ciss will also increase the apparent Qg for a given Summary. Figure 3471-3 illustrates the waveform and tests 1 through 4, condition A. Figure 3471-4 illustrates the waveform fortests 2, 4, 5, and 6, condition B. Only four of the six tests need be performed since the results of the remaining two are uniquelydetermined and may be calculated. Either condition A or condition B may be Condition Test 1, Q . g(th)a. Case temperature (TC): + Drain current: ID t 100 Off-state drain voltage (VDD): Equal to 50 percent of the device rated drain-source breakdown Load resistor (RL): Equal to Gate current (Ig): Constant gate current such that the transition from off-state to on-state is of the order of 50 value of Ig varies with die size and ranges from mA to 3 Gate to source voltage (Vg(th) min): The minimum rated gate-source threshold Minimum off-state gate charge (Qg(th)): A minimum and maximum limit shall be Test 2, Q . g(on)a. TC, ID, VDD, RL, Ig: Same as test 1 in VGS: The gate-source voltage specified for the rDS(on) test, V(on).c. On-state gate charge (Qg(on)): A minimum and maximum limit shall be Test 3, Q . gm(on) , ID, VDD, RL, Ig: Same as test 1 in : The maximum rated gate-source voltage, V(max). on-state gate charge (Qgm(on)): A minimum and maximum limit shall be Test 4, V . This test is to be performed on a dc parameter test set. = The continuous rated drain current at TC = + >> VGS. Normally VDD | 3 VGS is pulse width and duty factor are such that they do not materially affect the shall be specified as a maximum and = + Test 5, Q ; test 6, Q . No tests are required. The calculations in terms of the results of tests 1 through 4 are as gs gdfollows: b. Determine the fully on-state charge slope: c. Determine the Vgs axis intercept: b = V(on) - m Qg(on). Condition Test 2, Q . g(on) temperature (TC): + drain current (ID): The continuous rated drain current at TC = + drain voltage (VDD): Equal to 50 percent of the device rated drain-source breakdown drain load shall be such that the drain current will remain essentially current (Ig): Same as test 1 in , condition to source voltage V(on): Same as test 1 in , condition On-state gate charge (Qg(on)): A minimum and maximum limit shall be Test 4, V . , ID, VDD, Load, Ig: Same as test 2 in , condition : This is the gate plateau voltage where Qgs and Qgd are measured. This voltage is essentially constant during thedrain voltage transition when Qgd is supplied from the gate to the drain under constant Ig, ID Test 5, Q . , ID, VDD, Load, Ig: Same as test 2 in , condition : Equal to VGP at the specified : A minimum and maximum limit shall be Test 6, Q . , ID, VDD, Load, Ig: Same as test 2 in , condition : Equal to VGP at the specified : A minimum and maximum limit shall be Test 1, Q ; test 3, Q . No tests are required. The calculations in terms of the results of test 2, 4, 5, and 6 g(th) gm(on)are as follows: b. Determine the fully on-state charge slope:c. Determine the Vgs axis intercept:d. Calculate Qgm(on):METHOD 34714 MIL-STD-750DNOTES: 1. Condition B requires a constant drain current regulator. 2. Ig x t = 3471-1. Pulsed constant current 34715MIL-STD-750DNOTES: 1. This test method provides gate voltage as a monotonic function of gate charge. Charge or capacitance may beunambiguously specified at any gate voltage. Gate voltage assuring that the device is well into the on-state will result in veryreproducible measurements. For a given device, the gate charges at these voltages are independent of drain current and aweak function of the off-state voltage. 2. Condition B requires a constant current drain 3471-2. Practical gate charge test 34716MIL-STD-750DNOTES:1. Qg = VGP is measured by a dc test, same ID, VDS >> VGP (see ).3. V(max) and V(on) are specified voltages for charge measurements Qgm(on) and Qg(on).4. VGS(th) min is a specified voltage for measuring Qg(th).FIGURE 3471-3. Gate charge characterization showing measured 34717MIL-STD-750DFIGURE 3471-4. Gate charge, condition 34718MIL-STD-750DFIGURE 3471-5. Idealized gate charge waveforms, condition 34719/10MIL-STD-750DMETHOD TIME TEST1. Purpose. The purpose of this test is to measure the pulse response (td(on), tr, td(off), tf) of power MOSFET or IGBT devices underspecified conditions. For the IGBT, replace the drain and source MOSFET designations with collector and emitter IGBT designations, D= C and S = Test procedure. Monitor VGS and VDS versus time using the following notes and precautions. Refer to figures 3472-1 through3472-4 for Notes and method presumes that good engineering practice will be employed in the physical construction of the test circuit, , shortleads, good ground plane, minimum gate to drain mutual inductance, and appropriate high speed generators and value of RGS or RGE includes instrumentation resistive loading. RGEN and RGS RGE should be low enough in valuethat gate propagation effects are value of LDST or LCET, CGST or CGET, and CDST or CCET are understood to include those of the test fixture, circuitelements, instrumentation; and any added values, exclusive of the DUT. LDST or LCET shall not exceed 100 nH nor shall (CDST or CCET) or (CGST or CGET) exceed 100 pF. Devices with small die may need smaller values of LDST or LCET, CDST or CCET, and CGST or CGET. LDST, CDST, and CGST need not be measured when using figure 3472-3 and figure3472-4. When rCS(on) or rDS(on) is measured at a VGS or VGE of less than 10 V, then figure 3472-3 and figure 3472-4 donot circuit inductance need not be specified. With the DUT removed, the gate-source voltage waveform should be free ofanomalies that could materially affect the measurement. Inductance is difficult to measure accurately in a well designed testfixture. The gate drive common should be Kelvin connected to the device source circuit elements referred to in this method are lumped parameter representations whose values would be thoseobtained through the use of an RLC bridge using a 1 MHz test and current sources are to be interpreted as effective idealizations of active phrase "affect the measurement" is intended to mean that doubling a value will not affect results greater than the precisionof turn-off drain voltage overshoot should not be allowed to exceed the device rated drain-source breakdown voltage. Draincircuit ringing begins when the inductive time constant is 25 percent of the capacitive time constant. Ringing is particularlyserious when testing low voltage high current devices at high speeds. When the ratio LDST/R2 L(CDST + COSS)exceeds 10, test conditions may have to be adjusted to ensure that device breakdown is not instrument used for switching parameter measurement is an oscilloscope with input amplifiers and probes. The affect on riseand fall times can be estimated by the following relationship: (measurement rise time)2 = (actual rise time)2 + (amplifier rise time)2 + (probe rise time)2METHOD of 8MIL-STD-750Dj. When two channels with probes are involved in a measurement (turn-on and turn-off delays), the relative channel probe delaysshould not materially affect the measurement. Simultaneous viewing the same waveform using the two channel/probes is aneffective means of estimating otherwise specified, half rated drain voltage and rated drain current are mandatory conditions for measuring measuring rise time, VGS(on) shall be as specified on the input waveform. When measuring fall time VGS(off) shall bespecified on the input waveform. The input transition and drain voltage response detector shall have rise and fall responsetimes such that doubling these responses will not affect the results greater than the precision of measurement. The currentshall be sufficiently small so that doubling it does not affect test results greater than the precision of Test circuit and waveform: See figures 3472-1, 3472-2, 3472-3, and tables 3472-I and 3472-1. Switching time circuit parts list. ||||||| Part| No.| Value or size| Manufacturer| PIN|| | | | | |||||||| On-board supply| 1| 15 volts| Datel| UPM 15/100-A|| Voltage regulator| 1| TO-220 package| National| LM317|| Timer| 1| 8-pin DIP package| National| LM555|| Drivers| 1| 50 V, Hex1, p-channel| | IRFD9010||| 1| 100 V, Hexz, n-channel| | IRFD1ZO||| 2| 50 V, Hex2, p-channel| | IRFD9020||| 2| 50 V, Hex2, n-channel| | IRFD020|| Resistors 1/| 2| K:, .25 W, r1 percent| Dale| CMF604951FT0||| 1| 220 :, W, r1 percent| Dale| CMF602200FT0||| 1| 5 K: variable| Dale| 724, 5 K, r10 percent||| 1| M:, .25 W, r1 percent| Dale| CMF602204FT0||| 1| 360 :, .25 W, r1 percent| Dale| CMF603600FT0||| 1| 100 :, .25 W, r1 percent| Dale| CMF601000FT0|| Capacitors| 14| 1 PF, 50 V, r10 percent| Mallory| M30R105K5||| 10| .82 PF, 600 V, r10 percent| CRC| B55F824KXC||| 7| .15 PF, 50 V, r10 percent| Mallory| M30R154K5||| 4| .01 PF, 50 V, r10 percent| Mallory| M10R103K5||| 2| 22 pF, 600 V, r5 percent| AVX| AQ14BG220JU||| 1| 100 pF, 100 V, r10 percent| Sprague| TST10||| 1| 100 PF, 450 V, -10 percent,|||||| +5 percent| Sprague| 53D101F450JS6||| 1| .01 PF, 600 V, r5 percent| Sprague| 715P10356KD3|| DUT socket| 1| TO-3| Loranger| 3128-032-4225|| BNC| 3| PC board mount| Pomona Elect.| 4578|| Transformer| 1| Torroidal core| Micrometals| T5-12|| Banana plugs| 2| Standard uninsulated| Pomona| 3267|| Circuit board 2/| 1| " x "|||| | | | | |1/ All resistors are .062 inch ( mm) double-sided board with 3 ounces copper and 60/40 tin-lead of .0003 inch ( mm) 3472-2. Switching time circuit, component layout list. 1/ 2/ ||||| Label| Component| Value|| | | |||||| R1| Resistor| 220 :|| R2| Variable resistor| 5 K:|| R3| Resistor| M:|| R4| Resistor| 360 :|| R5| Resistor| 100 :|| R6| Gate resistor| Varies|| R7| Drain resistor| Varies|| C1, C2, C4, C26| Capacitor 50 V| .01 PF|| C3-C10, C12, C14| Capacitor| 1 PF|| C16, C18, C20, C22| Capacitor| 1 PF|| C11, C13, C15, C17| Capacitor| .15 PF|| C19, C21, C23| Capacitor| .15 PF|| C25| Capacitor| 100 pF|| C27, C29| Capacitor| 22 pF|| C28| Capacitor 600 V| .01 PF|| C30| Capacitor| 100 PF|| C31-C40| Capacitor| .82 PF|| Q1| MOSFET (4 pin DIP)| IRFD9010|| Q2, Q3| MOSFET (4 pin DIP)| IRFD9020|| Q4| MOSFET (4 pin DIP)| IRFD1ZO|| Q5, Q6| MOSFET (4 pin DIP)| IRFD020|| Q7| Regulator (TO220)| LM317|| Q8| Timer (8-pin DIP)| LM555|| T1| Iso. transformer| T5-12|| | | |1/ Figure 3472-3 board layout is an artist's view for an n-channel TO-3 package. The following companies will provide the circuit boards or a drawing of the exact board layout for a TO-3 as well as other packages such as the TO-39, TO-61, and TO-66: a. Integrated Technology Corporation 1228 N. Stadem Drive Tempe, AZ 85281 b. TEC 9800 Vesper Avenue Unit 28 Panorama City, CA 914022/ LDST, CDST, and CGST need not be measured when using these circuit boards derived from figures 3472-3 and 3472-1. Switching time test 3472-2. Switching time 3472-3. Board 3472-3. Board layout - 3472-4. Stand alone switching Summary. The following conditions shall be specified in the detail : Unless otherwise specified, case temperature = + : On-state drain current (see ). : Off-state drain voltage (see and ). : Nominally equal to VDD/ID (see ). : On-state gate voltage (see ). : Gate to source : Resistance looking back into the RECOVERY TIME (trr) AND RECOVERED CHARGE (Qrr)FOR POWER MOSFET (DRAIN-TO-SOURCE) AND POWER RECTIFIERS WITH trr d 100 ns1. Purpose. The purpose of this test is to determine the time required for the DUT to switch off when a reverse bias is applied afterthe DUT has been forward biased and to determine the charge recovered under the same Test Test condition A, reverse recovery time (t ). Monitor diode current versus time. If the DUT is a power MOSFET, the rrgate lead must be shorted to the source lead. Use the following notes and precautions as a guide. Refer to figures 3473-1 through3473-3 for Notes and method presumes that good engineering practice will be employed in the construction of the test circuit, , short leads,good ground plane, minimum inductance of the measuring loop, and minimum self-inductance (L1) of the current samplingresistor (R4). Also, appropriate high speed generators and measuring-loop inductance (LLOOP, see figure 3473-1) represents the net effect of all inductive elements, whetherlumped or distributed, , bonding wires, test fixture, circuit board foil, inductance of energy storage capacitors. The value ofLLOOP should be 100 nH or less. The reason for controlling this circuit parameter is that it, combined with diodecharacteristics, determines the value of turn-off reverse-voltage overshoot shall not be allowed to exceed the device rated breakdown voltage. Ringing andovershoot may become a problem with RLOOP < 2(L/C)1/2; where L = LLOOP. That is another reason for minimizing breakdown voltage, -V4 should be kept as self-inductance of the current-sample resistor R4 (see figure 3473-1) must be kept low relative to ta because theobserved values of ta and IRM increase with increasing self-inductance. Since the value of R4 is not specified, therecommended maximum inductance is expressed as a time constant (L1/R4) with a maximum value of ta(minimum)/10, whereta(minimum) is the lowest ta value to be measured. This ratio was chosen as a practical compromise and would yield anobserved ta which is 10 percent high ('ta = L1/R4). The IRM error is a function of the L1/R4 time constant and di/dt. For adi/dt of 100A/Ps the observed IRM would also be 10 percent high. 'IRM = L1/R4 di/dt of 100A/Ps was chosen so as to provide reasonably high signal levels and still not introduce the large IRM errorscaused by higher forward current (IF) used for this test shall be as specified at T = + values of ta, tb, and IRM are to be measured and recorded separately. trr = ta + forward current value must be specified, otherwise the ta and IRM values have little useful forward current generator consisting of Q1, Q2, R1, and R2 may be replaced with any functionally equivalent the current-ramp generator consisting of Q3, Q4, R3, and of Condition B, reverse recovered charge (Q ). This method is direct reading and therefore does not require an rroscilloscope. Use the following notes and precautions as a guide. Refer to figures 3473-4 and 3473-5 for Notes and method presumes that good engineering practice will be employed in the construction of the test circuit, , short leads,good ground plane, minimum inductance of the measuring loop. Also, appropriate high speed generators and measuring-loop inductance (LLOOP, see figure 3473-4) represents the net affect of all inductive elements in the loop,whether lumped or distributed, , DUT bonding wires, test fixture, circuit board foil, inductive component of energy storagecapacitors. The value of LLOOP should be 100 nH or turn-off reverse-voltage overshoot shall not be allowed to exceed the device rated breakdown voltage. Ringing andovershoot may become a problem when RLOOP < 2(L/C)1/2; where L = breakdown voltage, -V4 should be kept as di/dt of 100A/Ps was chosen as a compromise between having reasonably high signal levels for the faster devices andthe need to keep the reverse voltage as low as possible. Higher di/dt requires a higher reverse voltage to overcome the dropacross forward current (IF) used for this test shall be as specified at + capacitor C2 (see figure 3473-4) shall be large enough so that there is no appreciable voltage drop across it. Reducingits value by 50 percent shall not change the reading by more than the required measurement current meter across C2 should have as low a resistance as possible. Doubling the resistance shall not change thereading by more than the required measurement accuracy. A good compromise would be a digital ammeter with a full scaledrop of volt. If the reverse bias supply is 30 volts, the maximum meter potential differences is then less than one percentof supply recommended pulse repetition rate is 1 kHz r5 forward current generator consisting of Q1, Q2, R1, and R2 may be replaced by any functionally equivalent the reverse current-ramp generator consisting of Q3, Q4, R3, and t1 > = 5 ta (max) t2 > trr t3 > 0 amplitude controls forward current (If). amplitude controls is self inductance of (max) is longest ta to be (min) is shortest ta to be 3473-1. t test circuit. _rr_________METHOD 3473-2. Generalized reverse recovery 3473-3. Suggested board layout for low L /R . 1 4Bottom resistor current flow is in opposite direction of top resistor current flow, providing magnetic field cancellation. Sense lead to centerconductor of probe jack exits at right angle to resistor axes and is located between the resistor layers; five on top layer and five on :1. D1 provides forward current path to D2 steers reverse signal current into integrating capacitor (C2).3. V1 amplitude controls forward current (If).4. V2 amplitude controls t1 > = 5 ta (max); ta (max) is the highest ta to be t2 > t3 > D1 is a low voltage Schottky D2 must have a much lower recovered charge than the value being measured. 10. Qrr = IS PRR; where PRR is pulse repetition rate. 11. di/dt = 100 3473-4. Q test circuit. rrMETHOD 3473-5. Typical t waveform (for mnemonic reference only). _ rr_________________________________METHO D Summary. Unless otherwise specified in the detail specification, the following conditions shall : Case temperature = + : As specified at + : 100 : Reverse-ramp power supply : As OPERATING AREA FOR POWER MOSFET'sOR INSULATED GATE BIPOLAR TRANSISTORS1. Purpose. The purpose of this test is to verify the boundary of the SOA as constituted by the interdependency of the specifiedvoltage, current, power, and temperature in a temperature stable circuit. Deliberate consideration is given to the problem of unavoidablecase temperature rise during the test. For the IGBT, replace the drain and source MOSFET designations with collector and emitter IGBTdesignations, D = C and S = : Test power dissipation (watts). :Linear derating factor (W/qC). :Test current (amperes). :Test power supply voltage (volts). :Drain to source voltage (volts). :Junction temperature (qC). :Maximum rated junction temperature (qC). :Case temperature (qC). :Test pulse duration (seconds). :Maximum rated power dissipation (watts). :Rated SOA case temperature (qC). :Ambient temperature (qC). :Heat sink temperature (qC). :Junction to case thermal resistance (K/watt). :Case to heat sink thermal resistance (K/watt). :Heat sink to ambient thermal resistance (K/watt).2. Test circuit. See figure 3474-1. Circuit polarities shall be reversed for p-channel shall be a Kelvin contact resistor of five percent amplifier shall have a speed and accuracy such that the errors it produces will contribute less than a five percenterror to the voltage source shall have an accuracy of five shall have adequate speed and characteristics such that the accuracy of the measurement will not be affected by morethan five shall be maintained to within five shall be maintained to within five of 3MIL-STD-750DNOTE: Low inductance 3474-1. SOA test test accuracy shall be maintained to within 10 shall be selected to eliminate parasitic Procedure. Set the precision voltage source to ID x RS. Applied VDD to the circuit. Close S1 for tp Summary. Just like in any practical application, the junction temperature during an SOA test can be calculated by adding all of thetemperature drops in the system to the ambient temperature:RS d (Maximum rated gate voltage) ID not to exceed (.2 x maximum rated VDS)/IDTJ = TA + 'sink to ambient + 'case to sink + 'junction to caseUnder a controlled set of conditions, such as those that are encountered in an SOA test, the case temperature can be measured andtherefore known as a constant. This simplifies the expression substantially:TJ = TC + 'junction to caseTJ = TC + PD x RTJCBy substituting in the maximum rated junction temperature and rearranging the terms, the maximum power dissipation for this conditioncan be calculated: If a case temperature of TCRqC was chosen for the purpose of specifying the device SOA, then a derating factor "DF" can bedetermined:PDM can be any PDM from the SOA curves for that particular device type, either dc or pulsed. The maximum power dissipation for anycase temperature can now be readily calculated and used in an SOA testPD = PDM - (TC - TCR) x DFUnless otherwise specified in the detail specification, the following conditions shall = as = as calculated +20qC d TC d + shall be that which corresponds with the SOA curve being = as calculated shall be a value chosen from one of the SOA curves for that particular device either dc or = VDS + ID x TRANSCONDUCTANCE (PULSED DC METHOD) OF POWER MOSFET'sOR INSULATED GATE BIPOLAR TRANSISTORS1. Purpose. This method establishes a basic test circuit for the purpose of establishing forward transconductance (gFS) using pulseddc for the test conditions to enable measurements above the small signal (gFS) output current levels. The described method is adaptableto ATE where large ac test currents are often impractical. For the IGBT, replace the drain and source MOSFET designations withcollector and emitter IGBT designations, D = C and S = Procedure. The gate-source voltage (VGS1) is applied as necessary to achieve a specified drain-source current. ID1 shall be fivepercent minimum less than the value of ID used in specifying rDS(on) (normally 50 percent of rated dc current). The gate-source voltage(VGS1) is then decreased to achieve a second drain-source current (ID2). ID2 shall be five percent minimum below the ID1 used inspecifying rDS(on) . The drain-source voltage (VGS2)shall remain equal to the value specified for establishing :Where: 'VGS = VGS1 - VGS2NOTE:'VGS should not be set lower than volt or test equipment accuracy can adversely effect measurement. ID1 and ID2 canbe adjusted such that 'VGS is t volt. In all cases ID1 and ID2 should be adjusted so they are equally above and belowspecified current. The formula below can be used as initial reference point:If:then:The previous calculations can be used in establishing minimum 'VGS desired to achieve highest Test circuit. See figure Summary. Unless otherwise specified in the detail specification, the following conditions shall = ID continuous at TC = +25qC x = ID continuous at TC = +25qC x = 4 rDS(on) x ID continuous or as necessary to be in the active 'VGS t (on) as width d 300 otherwise specified, (TC) = (Temperature of case) = + of 2 MIL-STD-750DNOTES:1. Pulse the device according to MIL-STD-750. Resistor R1 shall be used to damp spurious oscillations that can occur(approximately 100 :).2. The device used for circuit illustration is an n-channel, enhancement-mode FET. The methodology described is not limited solelyto this type of device. For all other field effect devices where the power ratings are such that the dc method is the preferredmethod, the parameter symbols need only indicate the appropriate voltage or current When performing this test on a nonheat-sinked part, the following caution is applicable. The implementation of this test requiresthe use of repeated incremental steps of gate voltage, while measuring drain current. The number of steps and the duration ofeach step result is cumulative energy which may thermally overstress the part if it is not heat-sinked. A stepped program toperform this test will result in higher power dissipation during test of a unit requiring a high gate drive voltage than during test of aunit requiring a lesser gate drive R2 is a noninductive, current sensing resistor and is normally d :.FIGURE 3475-1. Forward transconductance 3476COMMUTATING DIODE FOR SAFE OPERATING AREA TEST PROCEDURE FORMEASURING DV/DT DURING REVERSE RECOVERY OF POWER MOSFETTRANSISTORS OR INSULATED GATE BIPOLAR TRANSISTORS1. Purpose. The purpose of this test method is to define a way for verifying the diode recovery stress capability of power MOSFETtransistors. For the IGBT, replace the MOSFET designators for drain and source with the IGBT designators for collector and emitter, D= C and S = E. The focus is on simplicity and Scope. This method covers all power transistors which have an internal diode capable of commutating current generated duringreverse :Gate drive :Gate to source circuit resistance at :Semiconductor junction :Gate generator voltage (volts) for drive :Supply :Maximum body diode forward Driver:A device is used in the lower portion of an "H" bridge (see figure 3476-1) and is an equivalent to the L(LOAD):Load inductor. Shall be of a large enough value such that the decay of current during the forwardconduction of the DUT is less than five percent of trv:Drain voltage rise time. Measured between 10 percent of VDD and 90 percent of VDD of the voltagewaveform. Limits shall be recorded during the test and a typical value shall be contained in the :Reverse recovery :Drain-source (BR)DSS:Breakdown voltage IGSS:Reverse gate current, drain shorted to :Zero gate voltage drain (ON):Static drain-source on state Circuit. Basic circuitry for testing this parameter is shown on figure 3476-1. Idealized waveforms are shown on figure may not be used. Stray capacitance and inductance, especially in the source of the drive transistor, must be basic principle of the circuit may not be altered, that is, the lower "H" bridge device must be equivalent to the DUT. The circuit mayoperate continuously, or, single shot, as long as the required test conditions are achieved. Gate drive to the driver may be any Theveninequivalent of that 34761 of 5MIL-STD-750DTo test continuously or single shot, the electrical sequence is almost the is turned on until current in L(LOAD) is higher than is turned off until current in DUT reaches IFM. The minimum time for DUT forward conduction is 5 Ps, or,10 times the rated maximum trr, whichever is testing "repetitively" then go back to step 1. Else, driver is turned on for the reverse recovery period of the deviceplus a minimum additional one microsecond. The DUT shall be monitored for VDS collapse during this additionaltime period, and gate drive to the driver transistor may be removed at any time a failure is the device operates with a low repetition rate, the device may not be exposed to sufficient energy to cause a catastrophic failure. Thecircuit must be equipped to either cause catastrophic failure or generate a failure signal in the event of a collapse of VDS during Specification details. The specification may take the form of a single point tabular specification, a graphical representation, or , a device will have both. This will allow for easy comparison of devices with the tabular specification, but still have the detail of thegraph available to the tabular specification will define a single point of operation. The following must be specified in the Gate drive impedance Gate generated voltage Maximum forward current Supply voltage Junction temperature V/ns graphical representation could take several different forms; for example, RG versus IFM, di/dt versus dv/dt, or IFM versus VDS. An example of RG versus IFM is shown on figure Acceptance criteria. If a specification requires that this test be performed for verification of a maximum limit, then the device VDSmust not collapse during or after reverse recovery and (in addition) must pass any specified parametric limits, as a minimum V(BR)DSS,IGSS, IDSS, and RDS(ON).METHOD 34762MIL-STD-750DFIGURE 3476-1. Body diode test 34763MIL-STD-750DFIGURE 3476-2. Body diode 34764MIL-STD-750DFIGURE 3476-3. Example of graphic 34765/6MIL-STD-750DMETHOD OF INSULATED GATE BIPOLAR TRANSISTORTOTAL SWITCHING LOSSES AND SWITCHING TIMES1. Purpose. This method defines the basic test circuitry and waveform definitions by which to measure the total switching losses of Scope. This method applies only to measurements of IGBT devices without an integral (BR)CES:Collector/emitter breakdown :Test :Gate to emitter :Gate drive series :Clamp voltage (80 percent rated V(BR)CES). :Time point where VCE is at 10 percent of the specified gate :Time point where iCE = 5 percent ICE (maximum). :Time point where VCE = 5 percent VCL when VCE is :Time point where VCE = 5 percent VCL when VCE is :t3 + 5 (on):Turn on delay :Rise td(off):Turn off delay :Fall :Turn on switching :Turn off switching :Total switching :Semiconductor junction :Gate drive of 4MIL-STD-750D4. Circuitry. Figure 3477-1 shows the basic test circuit. The circuit has to satisfy two fundamental circuit reflects the losses that are attributed to the IGBT only and is independent from those due to othercircuit components, like the freewheeling operation of the circuit shown on figure 3477-1 is as follows:The driver IGBT builds the test current in the inductor. When it is turned off, current flows in the zener. At thispoint, the switching time and switching energy test begins, by turning on and off the DUT. In its switching, theDUT will see the test current that is flowing into the inductor and the voltage across the zener, without any reverserecovery component from a freewheeling diode. This test can exercise the IGBT to its full voltage and currentwithout any spurious effect due to diode reverse drive duty cycle should be chosen such that Tj is not affected. Control of Tj is best done using Method. Figure 3477-2 shows the DUT current and voltage waveforms and test Energy loss during turn on. During turn on, the energy loss is defined as follows:(1) Refer to figure 3477-2 for t1 and Energy loss during turn off. During turn off, the energy loss is defined as follows:(2) Refer to figure 3477-2 for t3 and Total switching loss. The total switching loss is the sum of equations (1) and (2).(3) WTOT = WON + WOFF Switching time measurements. Switching time measurements, while not the preferred method of delineating between devices,may be determined using the rules below and as seen on figure td(on):The interval measured from the 10 percent point of the rising input pulse Vg and the 10percent rise of the output current tr:The interval measured from the 10 percent to the 90 percent point of the rising outputcurrent td(off):The interval measured from the 90 percent point of the falling input pulse Vg to the 90percent point of the falling output current tf:The interval measured from the 90 percent to the 10 percent point of the falling outputcurrent Equipment. A modern high speed digitizing system is recommended. The measurement of WON or WOFF is accomplished byaccessing the output V(t) and I(t) waveforms, digitizing them, and transmitting the data to a computer where WON or WOFF is calculatedand the results displayed. Two factors of importance must be spacing must be short relative to transition times for accurate and repeatable relative V(t), I(t) channel delay must be known and accounted for in the computer program that does the pointby point multiplication and summation that determines either WON or WOFF (see figure 3477-2).7. : Clamp voltage :Maximum test current A : Gate to emitter voltage :Gate resistance :Junction temperature qCMETHOD 3477-1. Test 3477-2. Typical clamped inductive 3478POWER TRANSISTOR ELECTRICAL DOSE RATE TEST METHOD1. Purpose. This test method establishes a baseline methodology for characterizing high-voltage transistors to high gamma dose rateradiation and for establishing electrical criteria to evaluate key test fixture parameters. From this data, a valid comparison can then bemade between the device's response and its radiation data. Since power transistors are susceptible to radiation-inducedburnout/damage, this test method should be considered a destructive test. For the IGBT, replace the drain and source MOSFETdesignations with collector and emitter IGBT designations, D = C and S = Definitions. Definitions, symbols, and terms used in this method are provided transistor burnout: Burnout is defined as a condition that renders the power transistor nonfunctional, usually a result ofcurrent-induced avalanche and second breakdown. Identification is accomplished by observing the drain current duringirradiation and by verifying the device's performance after and terms:di/dt:Change in current with respect to time (amperes per second).dv/dt:Change in voltage with respect to time (volts per second).Ids:Measured current flowing into drain (amperes).Ls:Calculated stray inductance observed by the DUT's response (henrys).PW:Radiation pulse width defined by the full-width half-max (FWHM) measurement (seconds).RC:Time constant equal to the resistance times capacitanceRs:Calculated stray resistance observed by the DUT's response (ohms).Vds:Applied measured drain-to-source voltage (volts).Vgs:Applied measured gate-to-source voltage (volts).3. Test plan. A detailed test plan shall be prepared specifying, as a minimum, the following device types to be number of fixture characteristics of stray Rs and Ls: based upon previous data or calculations (see ). characterization required in accordance with detailed specifications before and after the radiation parameters to be description of test system ( , schematics, flow charts).METHOD 34781 of 7MIL-STD-750D4. Instrumentation. Instrumentation required to monitor and test the device to high gamma dose rate radiation will generally consist ofthe following type of or analog current or analog current or storage power Holding fixture. The holding fixture may be mandated by the test facility. Coordination between users and facility is an absolutenecessity. The fixture shall be capable of interfacing the power and signal lines between the test board and DUT, as well as, collimatingthe radiation beam to expose only the Test fixture. The test board shall be constructed to meet the following : Circuit layout and construction are critical. Circuit layout and construction shall be optimized to minimize strayLs and Rs effects presented to the DUT. Applicable gauge wires, ground planes, and materials shall be used to minimizethese effects of stray inductance and resistance. Wire lengths shall be kept to an absolute : Wires lengths connecting the DUT in excess of four inches ( mm) should be re-evaluated to determine shortest possible wire : Circuit components shall be chosen to optimize performance. Capacitors shall have high "Q" ratings reflectinghigh di/dt. The test circuit shall have multiple capacitors in parallel, minimizing the parasitic resistance presented by eachcapacitor while obtaining the required dv/dt response. DC current probes shall be passive having minimal "ac" insertionresistance. The current probe shall also be capable of measuring a large current without saturating its magnetic package: Circuit and device parameters will dictate the power transistor response to high gamma dose rate DUT shall be tested in the same package type that will be used in the system. If a different package type is used, thenelectrical, mechanical, and thermal properties of that package need to be considered and their effects accounted for in the circuit: Schematically, test circuits are shown on figure 3478-1 and representative waveforms are depicted on figure3478-2. Components and wiring shall not be placed directly in the radiation beam. An isolation resistor shall be placedbetween the "stiffening" capacitors and high-voltage power supply, minimizing its interaction with the DUT response. Theresistor value will depend on the RC time constant required to isolate interaction. Biasing of the gate shall be accomplishedusing an RC filtering or ballasting resistor network (see figure 3478-1a or 3478-1b), unless it is connected directly to thecommon source (see figure 3478-1c).CAUTION: Peak currents in excess of 1,000 amperes with di/dt in excess of 1,000 amperes per microsecond are 34782MIL-STD-750DFIGURE 3478-1a. Gate bias configuration 3478-1b. Gate bias configuration 3478-1c. No gate bias configuration : 1. C1: Consists of several small capacitors (typically .1 PF). 2. C2: Consists of several large capacitors (typically 200 PF). 3. R1: Drain isolation resistor (typically > 1 k:). 4. R2: Gate filter resistor (typically 1 k:). 5. C3: Gate filter capacitance (typically PF). 6. P1: Current probe (Pearson Model +11 or similar).METHOD 34783MIL-STD-750DFIGURE 3478-2. Actual test 34784MIL-STD-750D5. Procedure. Two essential requirements are outlined in this procedure that allow a meaningful analysis of a device's radiationresponse as compared to data obtained on a different test through below, the procedure to characterize power transistor to high gamma dose rate radiation and what data tocollect and record are below, there is a description for a technique to extract key electrical parameters, Ls and Rs, allowing the test fixture tobe characterized using the above radiation Sample size. A minimum of five samples per device type shall be tested to determine the dose rate response of each powertransistor type. All devices shall meet the electrical specifications required for that particular device type before initial Identification. In all cases, each test sample shall be individually marked to ensure that the test data can be traced to itscorresponding test Radiation radiation source shall be either a flash x-ray or a facility/source shall be capable of varying the dose rate levels to characterize the device's response to various dose minimum pulse width shall be performed using a 20 to 50 ns pulse width (FWHM). Dosimetry. Dosimetry shall be used to measure the actual dose in rad(Si) of the radiation pulse. Any dosimetry technique thatmeets ASTM standards (ASTM F526-77) may be Waveform recording. The voltage, Vds, and test current, Ids, shall be monitored before, during, and after each irradiation. Voltagein excess of the maximum input voltage of the recording device shall be Test conditions. The DUT shall be biased with the specified test conditions and verified for each irradiation. Drain and gatecurrent shall be monitored before, during, and after each exposure. The capacitive load across the drain/source shall maintain the drainbias voltage, Vds, during the exposure within r10 percent of that specified. The test shall not be repeated until the "stiffening" capacitorshave sufficiently recharged. All tests shall be performed at the required ambient : Some transistors may require a gate bias to turn the DUT "off" after the radiation Test LINAC/flash x-ray to desired pulse width and dose rates and perform initial beam holding fixture and test system DUT (precharacterized in accordance with detailed specification). and verify test voltage to gate (Vgs). and verify test voltage to drain (Vds). monitors to appropriate DUT to desired dose photocurrent (Ids) and Vds test information: Test conditions Vds and Vgs; actual dose rate, accumulated total dose, date, and other informationpertinent to survivability of test device: Check electrical parameters to determine any with new test conditions: Different Vds, dose rate, or Determination of stray inductance/resistance. Knowing the stray components, Ls and Rs, will provide a technique to compare testdata from different test fixtures and packages. Ls and Rs will limit the amount of current flow and the peak current observed by the the recorded photocurrent waveforms, the quantitative values of the stray resistance, Rs, and inductance, Ls, can beextracted for that test fixture and The stray fixture components may change with exposure to radiation, testing, or the inductance, Ls, from the relationship:andThe calculated inductance will be influenced by the series resistance; and, therefore, the value of the di/dt response shall be basedupon the change in primary photocurrent between its 0 percent to 10 percent response. The Ls value shall be determined from thisexperimental the resistance, Rs, from the relationship:The calculated resistance should be determined from the peak primary photocurrent response and its corresponding time. Usingiterative calculations, Rs shall be determined within r5 percent based upon this experimental Documentation. Test records shall be maintained by the experimenter. Test records shall include the type, item, and lot of test and operator's of radiation source and pulse of test system and of dosimetry techniques and bias voltage current 34786 dose rate Vds to induce dose rate Vds not to induce leakage currents before and after waveforms of pulse shape total Ambient test records and serial numbers, if electrical measurements after radiation Reporting. This documentation shall be used to prepare a summary describing the test system, data, results, and analysis. Thesummary shall include a description of the device, dc electrical parameters before and after testing, a statistic summary indicating thesample mean and standard deviation of each device type, plots of photocurrent versus dose rate at a specified Vds and Vgs, calculationsfor stray Ls and Rs for the test fixture for each device type or package type, and a general synopsis of the test 34787/8MIL-STD-750DMETHOD 3479SHORT CIRCUIT WITHSTAND TIME1. Purpose. In some circuits, such as motor drives, it is necessary for a semiconductor device to withstand a short circuit condition forshort periods of time. During such a condition, the current in the device is dependent on the gain of the device and the level of the drivesupplied. It is important for the designer to know how long a device can survive a short circuit condition with a given drive level. Faultdetect circuits can be designed to react within this time period. In some cases the junction temperature may exceed the maximum it does, the rating shall be nonrepetitive with a limit on the maximum number of events over the lifetime of the device. Otherwise, it willbe a repetitive rating. In the case of a nonrepetitive rating, the manufacturer shall perform adequate reliability testing so as to ensure thevalidity of this rating. For military specifications, the controlling document shall mandate such Scope. This method covers all power semiconductors or hybrids that can be turned off with a control terminal and which areintended for use as switching devices. Power MOSFET's, IGBT's, and bipolar transistors are examples of these :Junction temperature (qC). Its starting value shall be specified, and controlled to fivepercent at the beginning of the :Short circuit withstand time (seconds). Measured between the time the device drive risesabove 50 percent of its peak value, and when it falls below 50 percent of its peak :Nominal short circuit voltage (volts). Must be maintained between +5 percent and -10percent of the specified value during the :Stray inductance of the output circuit shall be kept as low as is practical, in order to verifythis the maximum value of LS shall be a condition of the test called out on the detailedspecification of the device (see figure 3479-2). LS = V dt/di during the first 10 percent ofthe output current :One of the following:VDRIVE = Nominal drive voltage (volts).IDRIVE = Nominal drive current (amperes).This value must be maintained to within r5 percent of the specified value. In a graphicalrepresentation, various levels of "drive" may be specified, as shown on figure 3479-3. Thespeed of turn-off shall be such that avalanching the DUT is : The output impedance of the drive Circuitry. Electrical test circuitry is as shown on figure 3479-1. Drive circuitry must be appropriate for the device being tested,whether voltage or current driven. Care must be taken to minimize stray inductance in the output circuit in order to avoid limiting thecurrent during the test, or avalanching the device during turn off at the end of the 34791 of Procedure for measurement of short circuit withstand time (see figure 3479-2). : Apply test : Apply drive : Device drive reaches 50 percent of maximum : Remove drive : Device drive falls to 50 percent of maximum : Remove test Acceptance criteria. DC electrical test shall be conducted before and after the test. Exactly which parameters are to be measuredwill be device dependent, and shall be called out on the detail Specification. Tabular specification shall be as follows: tsc short circuit withstand time Ps at: short circuit voltage voltage (or current) V (or A) junction temperature output impedance stray inductance nHMETHOD 34792MIL-STD-750DFIGURE 3479-1. Test 3479-2. Short circuit withstand time 34793MIL-STD-750DFIGURE 3479-3. Sample graphical 34794MIL-STD-750DMETHOD 3490CLAMPED INDUCTIVE SWITCHING SAFE OPERATING AREA FORMOS GATED POWER TRANSISTORS1. Purpose. To define a method for verifying the inductive switching SOA for MOS gated power transistors, to assure devices are freefrom latch Scope. This method includes all power MOSFETs and IGBTs used in switching applications for power supplies and Circuitry. As shown on figure 3490-1, a simple inductive load circuit is employed. Drive circuitry applies a voltage to the DUT toachieve a specified current. The turn-off dv/dt is controlled by a gate resistor. A clamping diode or suppression device is used to limit themaximum voltage which occurs during turn-off. The clamping device must be located as close as possible to the DUT to minimizevoltage spikes due to stray inductance Definitions:TJ:Junction temperature (qC): Shall not exceed maximum rating of the :Ambient temperature (qC): Temperature used to heat the :Case temperature (qC): Temperature of the DUT as measured on the exterior of the package asclose as possible to the die :Collector supply voltage, :Clamping : Collector to emitter voltage gate shorted to : Source to drain voltage gate shorted to :Maximum off-state voltage measure at the DUT which is caused by stray inductance between theDUT and the voltage suppressor. VDM is due to L di/dt generated during :Load current through inductor and :Drive voltage from a voltage source used to turn-on and turn-off the MOS DUT to achieve a :Resistor in series with the gate which is used to limit turn-off dv/dt during :Change in voltage during turn-on and turn-off measured between 75 percent and 25 percent of totalclamp voltage during :Pulse width between turn-on and turn-off of :Stray series inductance due to layout of :Series 34901 of 3MIL-STD-750D5. Specification conditions. The following conditions shall be specified in the detail specification: = :V/Ps :Number of Acceptance degradation of blocking voltage at the end of test shall be or reduction of IL shall not be must meet group A, subgroup 2 Comments and resistor or gate drive source must be as close as possible to the DUT to minimize oscillations during resistor valve or gate drive is selected to assure minimum peak dv/dt is clamping device should be as close as possible to the DUT to minimize voltage over shoot. A generalguideline is VCF should not exceed 110 percent of VDM and must be less than avalanche breakdown of should be selected to assure peak current is reached. The IC will not be reached if too large of an inductor precautions should be taken when testing high voltage devices and rules and regulations for handling highvoltage devices should be 34902MIL-STD-750DFIGURE 3490-1. Inductive load : 1. Vclamp (in a clamped inductive-load switching circuit) or V(BR)DSX (in an unclamped circuit) is the peak off-state. 2. Drain and source references for MOSFETs are equivalent to collector and emitter references for 3490-2. Inductive load 34903MIL-STD-750D3500 SeriesElectrical characteristics tests for Gallium Arsenide transistorsMIL-STD-750DMETHOD 3501BREAKDOWN VOLTAGE, DRAIN TO SOURCE1. Purpose. The purpose of this test is to determine if the breakdown voltage of the gallium arsenide field-effect transistor under thespecified conditions is greater than the specified minimum Test circuit. See figure 3501-1. NOTE:The ammeter shall present essentially a short circuit to the terminals between which the current is being measured orthe voltmeter readings shall be corrected for the drop across the 3501-1. Test Procedure. A negative (reverse) voltage shall be applied to the gate, with the specified bias condition (condition A) applied, then apositive voltage applied to the drain. The device is acceptable if the gate current 1/ is less than the maximum specified with the voltagebias conditions on the gate and drain as specified in the detail specification. With the specified gate and drain voltages, if the specifiedmaximum gate current is exceeded, the device shall be considered a Summary. The following conditions shall be specified in the detail current (see 3). bias condition is gate to source and drain to source - reverse bias (specify bias voltages).____1/ Iq - - - - - Breakdown voltage as determined by maximum. Allowed gate current, with the specified bias condition applied from gate to source and drain to 35011/2MIL-STD-750DMETHOD 3505MAXIMUM AVAILABLE GAIN OF A GaAs FET1. Purpose. This method establishes a basic test circuit for the purpose of determining the associated gain of a gallium arsenidefield-effect transistor (FET).2. Procedure. Configure the test setup as shown on figure 3505-1. First apply the gate voltage (VGS) then apply the drain voltage (VDS). Adjust the gate voltage so that the FET is biased at the specified operating point as noted in the detail specification, such as IDS =50 percent of IDSS. Adjust the input and output tuners so that the transistor exhibits maximum output power and near maximum gain,that is, the transistor's gain must not be compressed more than 2 dB. The input power level is then reduced by at least 10 dB. At thisreduced input signal level, the small signal gain is defined as :G1dB = G0 - dB (Associated gain at the 1 dB compression point).The gain of the FET (output power/input power in dB) is recorded as the input power is increased in 1 dB increments. When themeasured gain of the FET is less than or equal to G1dB, as calculated above, the output power is recorded and this value represents the1 dB compression point (P1dB) power level and is used in determining the pass/fail status of the DUT in accordance with the valuespecified in the detail Test circuit. See figure Summary. Unless otherwise specified in the detail specification, the following condition shall apply: TC = (Temperature of case) =+ 3505-1. Test 35051/2MIL-STD-750DMETHOD 35101 dB COMPRESSION POINT OF A GaAs FET1. Purpose. This method establishes a basic test circuit for the purpose of determining the 1 dB compression point of a galliumarsenide Procedure. Configure the test setup as shown on figure 3510-1. To prevent damage to the DUT, first apply the gate voltage (VGS)then apply the drain voltage (VDS). Adjust the gate voltage so the FET is biased at the specified operating point as noted in the detailspecification, such as IDS = 50 percent of IDSS. Adjust the input power to the level and frequency given in the detail specification; adjustthe input and output tuners so the transistor exhibits maximum output power while its gain remains within 2 dB of the manufacturer'sspecified minimum gain for the part and while the gate current remains within the range specified in the detail specification. The gatecurrent must also remain within the range specified in the detail specification. The input power level is then reduced by 10 dB or somegreater amount specified in the detail specification. At this reduced input signal level the small signal gain is defined as G0. Calculation: G1dB = G0 = gain of the FET (output power/input power in dB) is recorded as the input power is increased in increments of 1 dB decreasing dB, or smaller, as G1dB is approached. When the gain of the FET is less than or equal to G1dB, as calculated above, the output isrecorded and this value represents the 1 dB compression point (P1dB) and is used in determining the pass/fail status of the DUT inaccordance with the value specified in the detail Test circuit. See figure Summary. Unless otherwise specified in the detail specification, the following condition shall apply: (TC) = (Temperature of case)= + 3510-1. Test 35101/2MIL-STD-750DMETHOD 3570GaAs FET FORWARD GAIN (Mag S21)1. Purpose. This method establishes a basic test method, test setup, and procedure for measuring the forward gain (Magnitude ofS21) of GaAs Procedure. Configure and calibrate the test setup as shown on figure 3570-1. To prevent damage to the DUT, first apply the gatevoltage (VGS) and then apply the drain voltage (VDS) to the bias levels specified in the detail specification. Adjust the gate voltage sothat the DUT is biased at the specified operating point, such as IDS = 50 percent of IDSS. Record the DUT's magnitude of S21 (in dB)using the network analyzer as shown on figure Test circuit. See figure Summary. Unless otherwise specified in the detail specification, the following condition shall apply: (TC) = (Temperature of case)= + 3570-1. Parameter test 35701/2MIL-STD-750DMETHOD 3575FORWARD TRANSCONDUCTANCE1. Purpose. This method establishes a basic test circuit for the purpose of establishing forward transconductance gm for galliumarsenide field-effect Procedure. The gate to source voltage (Vg1) is applied as necessary to achieve the specified drain to source current (IDS1). Thegate to source voltage is reduced gradually or increased gradually by volts (Vg2) and the drain to source current is measured (IDS2). The transconductance (gm) is calculated using the following formula:Calculation:3. Test circuit. See figure Summary. Unless otherwise specified in the detail specification, the following conditions shall = IDSS r10 percent otherwise specified, TC = (Temperature of case) = +25qC. NOTE:The ammeter shall present essentially a short circuit to the terminals between which the current is being measured or thevoltmeter readings shall be corrected for the drop across the 3575-1. Forward transconductance 35751/2MIL-STD-750D4000 SeriesElectrical characteristics test for diodesMIL-STD-750DMETHOD 4000CONDITIONS FOR MEASUREMENT OF DIODE STATIC PARAMETERS1. Purpose. When measuring a temperature-sensitive static parameter under conditions such that the product of the applied voltageand current at the test point produces a power dissipation level that will cause significant heating of the junction, the measured result maybe subject to errors due to thermal or transient effects. In order to avoid such errors, the measurement should be made under Steady state dc measurements. When making measurements under conditions of steady state dc, a condition of thermalequilibrium may be considered to have been achieved if halving the time between the application of power and the taking of the readingcauses no error in the indicated results within the required accuracy of measurement. For these purposes very long pulses or stepfunctions may be considered as steady state dc. When appropriate, the mounting conditions (TL or TC) or the thermal resistance(reference point to ambient RTCA or RTLA) shall be Pulse measurements. When a measurement is made under pulse conditions, the point of measurement after the start of the pulseshall be chosen such that it is long enough to charge interconnecting test cable capacitance, avoid electrical transient effects, and shortenough to avoid heating effects. This can be ensured if halving the minimum selected time, or doubling the maximum selected time, willnot produce errors beyond the defined accuracy of the measurement. The pulse measurement may be intended to correlate to a steadystate dc measurement, provided that a correlation has been 40001/2MIL-STD-750DMETHOD Purpose. The purpose of this test is to measure the capacitance across the device terminals under specified dc bias and ac Test circuit. See figure 4001-1. NOTE: Both dc bias and ac signal sources may be incorporated in the capacitance bridge. The dcbias source should be properly isolated, preferably with an inductance L in series andhave negligible capacitance compared to the DUT. The reactance of C must be negligiblecompared to the reactance of the DUT, at the frequency of measurement. Impedance ofvoltmeter should be at least 10 times that of the 4001-1. Test circuit for Procedure. The dc voltage source shall be adjusted to the specified bias voltage. The ac small signal voltage shall be adjusted tothe specified frequency for the capacitance measurement. The bridge shall be nulled and adjusted for zero capacitance reading just priorto insertion of the DUT to eliminate error from external Summary. The following conditions shall be specified in the detail bias VOLTAGE1. Purpose. The purpose of this test is to measure the voltage across the device when a specified current flows through the device inthe forward Test circuit. See figure :When specified, switch SW1 shall consist of either an electronic switch or a pulsegenerator to provide pulses of short-duty cycle to minimize device heating. When pulsetechniques are used, suitable peak-reading methods shall be used to measure theparameters of pulse amplitude, frequency, duty cycle, and pulse width. When dctechniques are used, device thermal equilibrium shall be achieved before themeasurement is 4011-1. Test circuit for forward DC method. The specified test current (IF) shall be adjusted by varying either the variable voltage source or the resistor (R). Thevalue of IF shall be measured using an ammeter. The forward voltage (VF) shall be measured using a dc voltmeter. The voltmeterconnections shall be made at specified points on the device and always within the current connection Pulse method. An oscilloscope shall be used to measure the pulse characteristics. The pulse generator or electronic switch shallbe adjusted to achieve the specified amplitude, frequency, and pulse width values. Device current (IF) may be determined by V peak X duty cyclemeasuring the voltage drop across a known value of resistor (R) where IF = -------------------------- RAfter adjusting pulse level to correct value for required IF, measure forward voltage Curve tracer method. A Tektronix Model 576 or equivalent curve tracer shall be used. The device shall be tested by applying apositive voltage to the anode and limiting the current to within the manufacturer's ratings for IF. The forward voltage may be determinedby observing the curve tracer waveform at the specified Summary. The following conditions shall be specified in the detail current (IF). voltage (VF). cycle and pulse width, when pulse techniques are CURRENT LEAKAGE1. Purpose. The purpose of this test is to measure the reverse current leakage through a device at a specified reverse voltage using adc method or an ac method, as DC Test circuit. See figure 4016-1. NOTE:To assure accurate measurement of reverse leakage current, the voltage drop across the ammeter shall be subtractedfrom the measured value of reverse voltage. Resistor (R) shall be chosen to limit the current flow in the event thedevice goes into reverse 4016-1. Test circuit for reverse current leakage (dc method). Reverse current. The dc voltage shall be adjusted to the specified value by voltmeter (V) and the reverse current (IR) shall bemeasured by current meter (I).3. AC Test circuit. See figure 4016-2. Test circuit for reverse current leakage (ac method).METHOD of Reverse current. A Tektronix 576 curve tracer or equivalent shall be used. The curve tracer supply shall be adjusted to obtainthe specified peak reverse voltage across the device. Current and voltage shall be measured on the curve Summary. The following conditions shall be specified in the detail or ac voltage (dc method) or peak reverse voltage (ac method). resistance of minimum heat dissipator on which device is mounted in qC/W (where applicable).METHOD VOLTAGE (DIODES)1. Purpose. The purpose of this test is to determine if the breakdown voltage of the device is greater than the specified minimum Test circuit. The resistance R is a current-limiting resistance and is chosen to avoid excessive current flowing through the device. NOTE:The ammeter shall present essentially a short-circuit to the terminals between which the current is being measured orthe voltmeter readings shall be corrected for the drop across the 4021-1. Test circuit for breakdown voltage (diodes).3. Procedure. The reverse current shall be adjusted from zero until either the minimum limit for breakdown voltage or the specifiedtest current is reached. The device is acceptable if the specified minimum limit for BV is reached before the test current reaches thespecified value. If the specified test current is reached first, the device is Summary. The test current (see 3.) shall be specified in the detail 4022BREAKDOWN VOLTAGE(VOLTAGE REGULATORS AND VOLTAGE-REFERENCE DIODES)1. Purpose. This test is designed to measure the breakdown voltage of voltage regulator and voltage-reference devices under thespecified Test circuit. See figure 4022-1. NOTE:The voltmeter being used to measure the terminal voltage should present an open circuit to the terminals across whichthe voltage is being 4022-1. Test circuit for breakdown voltage (voltage regulators and voltage-reference diodes).3. Procedure. The reverse current shall be adjusted from zero until the specified test current is reached. The specified test currentshall remain applied for the specified time to approach thermal equilibrium with the device mounted as specified in the individualspecification. The breakdown voltage shall then be read from the Summary. The following conditions shall be specified in the detail current (see 3.). after application of test current when breakdown voltage shall be of 40221/2MIL-STD-750DMETHOD 4023SCOPE DISPLAY1. Purpose. The purpose of this test is to define criteria for inspection of the dynamic reverse characteristics of rectifiers, switching,and zener diodes when viewed on a curve tracer. This inspection criteria may not be applicable to specific rectifier designs where thedevice is not intended to be driven into avalanche breakdown, or where the detail specification has not provided for this devices requiring stable or sharp and stable breakdown characteristics. NOTE: Since low voltage zeners do not inherentlyhave, and some other devices may not have a "sharp" breakdown, specific exceptions in requirements are also condition A, stable (only) types, figures 4023-4 through 4023-11 shall condition B, sharp and stable types, figures 4023-2 through 4023-11 shall apply. The ideal sharp and stable trace is onewhich exhibits a single horizontal line up to the point of breakdown, then transitions vertically to form a 90 degree angle whilemaintaining the single line (see figure 4023-1). Deviations from this ideal, which are not specifically allowed in this method ordetail, specification shall be cause for rejection of the DUT. The following depictions (figures 4023-2 through 4023-11) havebeen compiled to describe commonly observed faults. Tolerances from acceptable devices have been assigned curve tracer presentation shall be configured so that the horizontal axis shall be calibrated in volts per divisionand the vertical axis shall be calibrated in amperes per division (or fractions thereof). The vertical and horizontalaxis of the curve tracer presentation will be graduated into 8 or 10 divisions, each representing a precalibratedincrement of current or series load resistor shall be used to limit the device reverse current and prevent device damage. This typicalresistance should be approximately one quarter or more of the device resistance at the breakdown specification,when the curve trace set-up permits. Example: A device to be observed at IBR of 100 PA which is specified to be400 volts minimum, would have a series resistance chosen according to the following: R t (400 / ), therefore R t 1 M:The curve tracer peak voltage (VCT) may also require limitation, particularly if the series load resistance describedcannot be achieved. See figure 4023-1 and e. below for typical load line relationships to assure safe reversecurrent trace should occur in the first and third quadrant of the display and be slowly adjusted from zero volts to attainthe specified current with the maximum amount of resolution for determination of trace characteristics. The DUTshall be held under breakdown conditions for at least one second to ensure freedom from intermittent instability forbreakdown drift. NOTE: All figures herein are shown in the first vertical and horizontal sensitivity shall be adjusted on the curve tracer to provide a rendition of the completetrace to the specified current. Horizontal and vertical sensitivity shall be adjusted to provide a trace occupying noless than 50 percent of the available 40231 of curve trace voltage shall not be simply set at a predetermined value and snapped on instantaneously. Thismay be done only if the product to be tested is known to have a sufficiently narrow breakdown voltage (VBR) rangewith a predetermined series (load line) resistor setting (see b.) and described below, to assure that the device willnot be overpowered. This is typically the case for zener diodes prescreened on VZ (or VBR). The peak opencircuit supply voltage of the curve tracer (VCT) may then be adjusted such that the VCT setting can provide nomore current (IBR or IZ) than that required for avalanche breakdown, taking into account the series load resistance"R" in figure 4023-1. Unless otherwise specified, these relationships may be calculated by: VCT - VBR IBR = ----------------, and VCT = IBRR + VBR RThe resistance "R" may be determined by: VCT - VBR R = ---------------- IBRThe VBR (or VZ) utilized in this equation should be the minimum expected so as to always maximize the R for deviation from the desired characteristics described in this method or detail specification must begranted by the qualifying activity. If a particular rejectable trace described is expected in a manufacturer's normalprocess, it must be identified and explained during device conformance/ qualification. Devices exhibiting theexceptional trace characteristic must be present in the conformance/qualification lot to establish Summary. The following condition shall be specified in the detail specification: Test condition to be 40232MIL-STD-750DThis ideal trace exhibits none of the characteristics described on the figures below. Also, illustrated are the basic curve traceradjustments and relation for a safe maximum operating current (IBR) with the series load resistor (R) versus peak open circuit voltage (VCT) and device breakdown voltage (VBR).FIGURE 4023-1. Ideal knee area is the area in which the trace transitions from the horizontal to the vertical. Unless otherwise specified, this area shouldnot require more than 10 percent of the total horizontal voltage component being viewed, or more than 20 percent of the specified applicable to fast, ultrafast, and schottky rectifiers or low voltage zeners d 10 4023-2. Soft 40233MIL-STD-750DThe vertical component of the trace should remain stable in the horizontal axis. An undesirable drift is defined as greater than a 10percent increase or 2 percent decrease in actual breakdown voltage up to 1,500 volts. If over 1,500 volts, the allowable drift should beseparately 4023-3. slope shall be less than 10 percent of VBR when viewed between 20 percent to 100 percent of the specified IBR or IZ. Low voltagezeners below volts are in exception to this requirement; also or other devices, as may be 4023-4. 40234MIL-STD-750DThe double break is the area in which the trace transitions from the horizontal to the vertical. Unless otherwise specified, this area shouldnot occupy more than 10 percent of the total horizontal voltage component being viewed, or more than 20 percent of the specified IBR orIZT. This requirement is not applicable to ultrafast or schottky rectifiers, and low voltage zeners d 10 4023-5. Double break (reject criteria for sharp knee devices).For rectifiers and zeners the region at the knee may display a secondary trace no more than 5 percent of the total voltage of the DUT (seedetail).FIGURE 4023-6. Double 40235MIL-STD-750DAny jittery movement of the trace in any direction, not caused by power line voltage fluctuations, must not 4023-7. Unstable (jitter).The vertical component must not depart from a single vertical line, except as allowed on figures 4023-5 and 4023-8. 40236MIL-STD-750DThe vertical component must not decrease its value abruptly by 2 percent or more of 4023-9. Snap back - collapsing V . BRLeakage current (vertical) must not degrade from an initial 4023-10. 40237MIL-STD-750DInstability (arcing) appearing at or near the specified IBR region on the vertical trace (such as may be coincident with visible sparkingactivity within the device die region) must not be present. Noise at or near the knee is permissible, such as typically observed onavalanche-zener 4023-11. 40238MIL-STD-750DMETHOD RECOVERY VOLTAGE AND TIME1. Purpose. This test is intended to measure the forward voltage and recovery time of the device. A device reveals an excessivetransient forward voltage when it is switched rapidly into the forward conductance region. The amplitude and time duration of this voltagepeak can be measured by observing the voltage waveform across the device when a flat-top pulse of the specified amplitude, rise time,pulse width and frequency are applied to the Test circuit. See figure forward transient test circuit shown on figure 4026-1 is used in conjunction with a pulse generator and anoutput sensing device. Care should be taken to minimize lead length where lead inductance might cause ringing inthe test The value of resistor Rp shall be chosen to optimize the impedance match between pulse generator and testcircuit, thereby minimizing the ringing in the test 4026-1. Test circuit for forward recovery voltage and of 2MIL-STD-750D3. Procedure. Test shall be performed using the input A:(1)IF amplitude: As specified.(2)Rise time = 10 ns or as specified.(3)Pulse width t1 t 10X specified response time.(4)Generator resistance RS t 20 RF (RF = VF/IF at specified IF).(5)Pulse frequency shall be such that a reduction in frequency shall result in no change in forward detector input impedance, Z t 100 Summary. The following conditions shall be specified in the detail of input waveform A (see ). time if other than 10 nanoseconds (see ). recovery voltage V(peak) chosen to terminate the forward recovery time measurement (see figure 4026-1). following measurements should be made:Forward recovery time (tfr) (measured from the time forward voltage becomes positive to the time that forward voltagerecovers to a specified vfr) (see figure 4026-1). peak forward voltage V(peak) (see figure 4026-1). This symbol is interchangeable with RECOVERY CHARACTERISTICS1. Purpose. The purpose of this test is to measure the reverse recovery time and other specified recovery characteristics related tosignal, switching, and rectifier diodes by observing the reverse transient current versus time when switching from a specified forwardcurrent to a reverse biased state in a specified General guide for selecting appropriate condition. Four conditions are given to include recommended practice for the range ofdiodes considered. A general guide for selecting the appropriate condition letter diodes with reverse recovery time less than 6 to medium current rectifiers with maximum specified recovery times of 50 to 3,000 current rectifiers with maximum specified recovery times of 350 ns or rectifiers, particularly on new , detailed guidance is given under each condition Test condition A. This condition is particularly relevant to low-current, signal diodes faster than 6 ns and tested at 10 mA. However,it is practicable for measurements up to 20 ns and 100 Circuit notes for condition time of the reverse voltage pulse across a noninductive calibration resistor in place of the DUT shall be less than 20percent of the recovery time of the DUT, for greatest rise time shall be less than 20 percent of device recovery time, for greatest coaxial networks and terminations shall be employed to ensure against error-producing pulse > 10 otherwise specified, RL = ZPG + ZSCOPE = 100 :. > 10 PW > 2 x maximum specified trr (see figure 4031-1.)METHOD of 12MIL-STD-750DNOTE: The test circuit shall comply with the test conditions as stated under PW = Pulse width of reverse voltage pulse (see figure 4031-2). RL = Load resistance. C = Coupling 4031-1. Test circuit for condition Procedure for condition A. The specified forward current shall be adjusted by resistor R and the + supply. Voltage E, developedacross the 50 ohm oscilloscope input impedance shall be measured. Specified forward current shall be calculated by the expression IF =E/50. The time duration of IF shall be at least 10 times the device recovery time. The oscilloscope trace deflection above zero referenceshall be adjusted by the oscilloscope vertical sensitivity to produce an amplitude of 2 cm minimum vertical deflection. Adjustment of thereverse transient current (IRM) shall be made by varying the pulse generator output, observing the voltage E across the 50 ohmoscilloscope input impedance, and calculating IRM by the expression I = E/50. When reverse bias voltage VR is specified, and IRM isnot, the DUT shall be replaced with a shorting bar and IRM shall be calculated by the expression VR/50 (see figure 4031-2.) Summary for condition A. The following conditions shall be specified in the detail current, current IRM (preferred), or reverse voltage (optional alternative). resistance, if other than 100 : (this is the sum of ZPG and ZSCOPE). temperature in impedance, if other than 50 :. current measuring point, iR(REC), if different from 10 percent of following measurement shall be made: trr (see figure 4031-2).METHOD 4031-2. Response pulse waveforms for condition Test condition B. (See suggested conditions below ( , B1, B2).) This condition is particularly relevant to medium current (axialand similar) types of standard and fast rectifiers with maximum specified recovery times between 50 and 3,000 ns that measured at peakforward currents greater than 100 mA and less than or equal to ampere. It is readily adapted to lower test currents. This test is alsoappropriate for devices with recovery times less than 50 ns that are measured at peak forward currents of 1A or less; below 25 ns, or athigher current, particular care must be used to achieve low loop inductance and low circuit rise times to achieve acceptable condition differs from condition D in that the reverse current (IRM) is limited by the test circuit, not by the 4031-I. Test condition B. | Designation (condition) | B1| B2| B3 | B4| B5|| | | | | | ||||||||| Test current, IF| | | | | || (amperes) ||||||| (see figure 4031-4) IRM | | | | | ||||||||| iR(REC)| | | | | |1 | | | | | ||||||||| Circuit RF| 33| 33| 50| 50| 1,200|| resistor 1/ ||||||| (ohms) RR| 9| 9| 15| 15| 200||||||||| R4| | | | | || | | | | | | 1/ Preferred nominal resistance values are shown; modification of RF and RR may be needed to achieve the rise time of and the IRM Circuit notes for condition B. The timing and test circuit of figure 4031-3A is a guide to that needed. An equivalent circuit may beused. Figure 4031-3B shows a suggested configuration for R4. Duty factor shall be 5 percent rise time of the reverse voltage pulse across a noninductive calibration resistor in place of DUT shall be less than 20percent of the recovery time of the oscilloscope rise time shall be less than 50 percent of the pulse generator rise and RF control forward current IF. t1 > 5 trr(max).V4 and RR control reverse current IRM. t2 > (max) is the longest to be measured. t3 > (min) is the shortest expected. L1/R4 < trr(min)/10. (L1 is the self inductance of R4)FIGURE 4031-3A. Test circuit for condition : 1. Resistor assembly R4 consists of 10 resistors (1 :, .25 W metal film), 5 on top and 5 on the bottom foils. The center of resistorbodies are not shown, and leads are shown dotted so that conducting foils may be more clearly shown. Bottom resistor currentflow L to R ( o) is opposite to top current flow R to L (m ), providing magnetic field cancellation. Sense lead to the centerconductor of the probe jack exits at right angle to resistor axes and is located between the top and bottom resistor layers. 2. Cross hatched circular areas show the connections between those top and bottom foil regions indicated by arrows. 3. To ground of circuit and probe. 4. To center conductor of miniature probe jack. 5. To cathode of 4031-3B. Suggested board layout for low L1/R4 for condition Procedure for condition B. Specified forward current (IF) shall be adjusted by varying positive voltage, V3. Reverse current (IRM)shall be controlled by varying the negative voltage, V4 (see figure 4031-4). With the DUT in place the circuit must be capable of higherthan specified IRM; the circuit, andnot the diode, must limit 4031-4. Current through DUT (condition B). Summary for condition B. The following conditions shall be specified in the detail condition ( , B1, B2) (see 3.) If not in table 4031-I, specify c, d, and temperature, if other than + current, current, IRM. NOTE: Specify c through --o only if not a resistances RF and RR. Designation in table measuring point, iR(REC).The following measurement shall be made: trr (see figure 4031-4).5. Test condition C. This test is intended for high current rectifiers with reverse recovery times equal to or greater than 350 ns andtested with peak forward currents equal to or greater than 10 4031-5. Circuit for measuring reverse recovery characteristics (condition C).NOTE: RS and CS are snubber components, when their use is specifiedMETHOD Circuit notes for condition Ca. The circuit is designed to simulate the commutation duty encountered in power rectifier diode circuits while also keeping averagepower dissipation low to minimize the need for thermal management. __b. The resistance of the and DUT loop (R2 and parasitics) is small, , 2S L/C much greater than R so the test current willessentially be sinusoidal, possessing a width of LC, a di/dt of V/L and a peak value of S L/C. The peak voltage across thecapacitor shall be as small as practicable to achieve the desired test conditions. The effects of reverse voltage magnitude on thetest device recovery characteristics are The minimum forward current pulse time (tp) shall be at least five times the recovery time (trr) of the DUT so that the di/dt will belinear and of the same value before and after current The oscilloscope rise time shall be less than 20 percernt of ta or tb (see figure 4031-6), whichever is The inductance of the current viewing resistor shall be extremely low, , microhenry. Abrupt recovery rectifiers (figure4031-6) can cause current oscillations which may be reduced by using a lower inductance current viewing resistor and byproperly terminating the oscilloscope cable. A current transformer 1/ with suitable rise time may be substituted for the currentviewing resistor. Rectifier diode RD2 provides a very low inductance path around SCR1 if the reverse recovery time of SCR1 isshorter than that of the DUT. An external SCR triggering source may be required to achieve stable A slight oscillation may appear on the waveform following device recovery. This may be reduced by reducing the current viewingresistor's inductance, or properly terminating the viewing cable. The oscillation, however, does not affect the test D2 and its circuit branch should provide a very low inductance path around the SCR if the reverse recovery time of the SCR isshorter than that of the R3 must be sufficiently large such that the SCR triggers only after the capacitor, C, has had ample time to charge to its desiredvalue. If stable triggering or ample charging is a problem, a momentary pushbutton switch may be inserted in line with R3 toprovide triggering. A pulse transformer technique is also acceptable in the triggering Procedure for condition C. C, L, and V are adjusted to obtain the specified test current di/dt and magnitude, IFM. The recoverytime for rectifier diodes is defined as trr = ta + tb (see figure 4031-6) ta is measured from the instant of current reversal to the instant thatcurrent reaches its peak reverse value IRM(REC) and tb is measured from IRM(REC) to the instant the straight line connecting IRM(REC) and IRM(REC) intercepts the zero current axis. The recovery time for devices with abrupt recovery characteristics isdefined in the same manner except tb is measured from IRM(REC) to the instant the test current waveform intercepts the zero currentaxis, if Pearson Electronics, Inc. or equivalent 4031-6. Test current waveforms for various types of rectifier diodes under test in the circuit for measuring reverse recovery Summary for condition The following conditions shall be specified in the detail specification:(1) Case temperature in qC.(2) Test repetition rate, in Hz.(3) Peak forward current, IFM, in amperes.(4) Rate of decrease of forward current, di/dt, in A/Ps.(5) Minimum test current pulse width, tp, in microseconds. (Duty cycle shall be d one percent).b. The following characteristics shall be specified for measurement in the detail specification as required:(1) Reverse recovery time (defined as trr = ta + tb), ta, tb.(2) Reverse recovery current, IRM(REC), in Test condition D. (See suggested conditions ( , D1, D2, D3) in table 4031-II.) This condition is intended for ultra-fast mediumcurrent rectifiers (axial and case mount, or equivalent styles) measured at IF t 1A and with reverse recovery time d 100 ns. With goodengineering practice, condition D can adequately measure trr down to about 10 ns; it can also utilize If up to at least 10 4031-II. Test condition D. ||||| Device ratings | Designation| Values for testing |||| (condition)|||| IO or IF (AV)| trr|| IF| di/dt|| (A) | (ns) | | (A) | (P/s) |||||||| 1 to 4| > 65 to 100| D1| 2| 100|||||||| to 20| > 65 to 100| D2| 6| 100|||||||| over 20| > 65 to 100| D3| 10| 100|||||||| 1 to 4| d 65| D4| 2| 200|||||||| to 20| d 65| D5| 6| 200|||||||| over 20 1/| d 65| D6| 10| 200|| | | | | | 1/ For devices with substantially higher rated current it is desirable to use test conditions for IF close to rated current, and higher values of Test circuit. Refer to figures 4031-7 and 4031-8 for timing and circuit details. Equivalent circuits may be used. The forwardcurrent generator consisting of Q1, Q2, R1, and R2 may be replaced with any functionally equivalent circuit. Likewise, the current-rampgenerator consisting of Q3, Q4, R3, and C1. The duty factor shall be d 5 method presumes that good engineering practice will be employed in the construction of the test circuit, , short leads,good ground plane, minimum inductance of the measuring loop and minimum self-inductance (L1) of the current samplingresistor (R4). Also, appropriate high speed generators and instruments must be measuring-loop inductance (LLOOP, see figure 4031-7) represents the net effect of all inductive elements, whetherlumped or distributed, , bonding wires, test fixture, circuit board foil, inductance of energy storage capacitors. The value ofLLOOP should be 100 nH or less. The reason for controlling this circuit parameter is that it, combined with diodecharacteristics including CT, determines the value of turn-off reverse-voltage overshoot shall not be allowed to exceed the device rated breakdown voltage. Ringing andovershoot may become a problem with RLOOP < 2 (L/C); where L = LLOOP. That is another reason for minimizing breakdown voltage, -V4 should be kept as low as practicable, especially when test low voltage devices. A value ofapproximately 30 volts is time constant of the self-inductance of the current-sample resistor R4 (see figure 4031-8) must be kept low relative to tabecause the observed values of ta and IRM increase with increasing self-inductance. Since the value of R4 is not specified,the recommended maximum inductance is expressed as a time constant (L1/R4) with a maximum value of ta (minimum)/10,where ta (minimum) is the lowest ta value expected. This ratio was chosen as a practical compromise and would yield anobserved ta which is 10 percent high ('ta = L1/R4). The IRM error is a function of the L1/R4 time constant and di/dt. For adi/dt of 100 A/Ps the observed IRM would also be 10 percent high. 'IRM = L1/R4 di/dt of 100 A/Ps was chosen so as to provide reasonably high signal levels and still not introduce the large IRM errorscaused by higher di/dt. Higher values of di/dt, without large errors, can be achieved with lower L1 amplitude controls forward current (IF). t1 > 5 ta(max).V2 amplitude controls di/dt. t2 > (max) is the longest ta to be measured. t3 > (min) is the shortest ta to be measured. L1/R4 < ta(min)/10. L1 is the self inductance of 4031-7. trr test circuit for condition : 1. Resistor assembly Rr is made from 10 resistors (1 :, .25 W metal film), 5 on top and 5 on the bottom foils. The center of resistorbodies are not shown, and leads are shown dotted so that conducting foils may be more clearly shown. Bottom resistor currentflow L or R ( o) is opposite to top resistor current flow R to L (m ), providing magnetic field cancellation. Sense lead to thecenter conductor of the probe jack exits at right angle to resistor axes and is located between the top and bottom resistor layers. 2. Crosses hatched circular areas show the connections between those top and bottom foil regions indicated by arrows. 3. To ground of circuit and probe. 4. To center conductor of miniature probe jack. 5. To cathode of 4031-8. Suggest board layout for low L1/R4 for condition Procedure for condition D. Adjust V1 for the specified forward current, IF. Adjust -V2 for the specified di/dt (see figures 4031-7and 4031-9). Summary for condition following conditions shall be specified:(1)Designation (condition, see table 4031-II). If another is desired, 4 and 5 must be specified. If another is desired, d ande must be specified.(2)-V4, reverse ramp power supply voltage.(3)TC, case temperature, if other than +25qC.(4)IF, .25 (minimum) of the continuous rated current is the suggested alternative (see table 4031-II).(5)di/dt, 100 A/Ps is the suggested alternative (see table 4031-II). following characteristics shall be specified for measurement:(1)Reverse recovery time, trr (see figure 4031-9).(2)IRM(REC) (see figure 4031-9) NOTE:An additional measurement, ta may be made if desired to compute tb = trr - ta, and the recovery softness factor, RSF = 4031-9. Generalized reverse recovery waveforms for condition "Q" FOR VOLTAGE VARIABLE CAPACITANCE DIODES1. Purpose. The purpose of this test is to measure the quality factor (Q) of the device. By definition, Q expresses the ratio ofreactance to effective resistance of the device, under rf signal conditions and specified dc bias Test circuit. See figure 4036-1. NOTE:The impedance of C1, C2, and L1, L2 shall be small and large, respectively, compared to the DUT at the frequency 4036-1. Test circuit for measuring Procedure. The test equipment shall be connected as shown in figure 4036-1. The dc bias supply shall be adjusted for thespecified voltage where Q is to be measured. Unless otherwise specified, the rf level shall be adjusted to 50 mV (rms). The parallelresistance Rp and capacitance Cp of the test device shall be measured using rf bridge methods. Unless otherwise specified, the point ofmeasurement shall be .062 inch ( mm) from the device body. Q shall be calculated using the following formula: Q = Summary. The following conditions shall be specified in the detail dc bias (VR). level if other than 50 mV (rms). "Q".METHOD EFFICIENCY1. Purpose. The purpose of this test is to measure rectification efficiency which is the ratio of dc output voltage to peak ac Test circuit. See figure :The voltmeter shall have a high impedance as compared with the load circuit of RL and 4041-1. Test circuit for rectification Procedure. The ac signal shall be adjusted to the specified frequency and signal level measured by means of peak readingvoltmeter (Vpk). The rectified output voltage shall be measured by means of voltmeter (VDC).4. Summary. The following conditions shall be specified in the detail capacitor (CL) and load resistor (RL). and amplitude of ac CURRENT, AVERAGE1. Purpose. This test is designed to measure the average reverse current through the device under the specified Test circuit. See figure 4046-1. NOTE: The reverse leakage current at each device D1 and D2 must be less than .05percent of the maximum allowable specified leakage current of the DUT. Inother respects, the devices D1 and D2 should be of the same type as the 4046-1. Test circuit for reverse current, Procedure. After thermal equilibrium, at the temperature specified, the specified voltage shall be Summary. The following conditions shall be specified in the detail temperature, when required (see 3.). voltage (see 3.).METHOD REVERSE BREAKDOWN IMPEDANCE1. Purpose. The purpose of this test is to measure the reverse breakdown impedance of the device under small-signal Test circuit. See figure : 1. The impedances of C1 and C2 shall be small compared to the DUT at the test frequency. 2. Voltmeters VAC and V2 shall be high input impedance rms types. 3. The resistance of R1 shall be large compared with the breakdown impedance being measured. 4. A low pass filter may be installed in series with the ac signal 4051-1. Test circuit for small-signal reverse breakdown Procedure. The specified reverse direct current shall be applied to the DUT. An ac signal in the frequency range of 45 through1,000 Hz shall be applied to the DUT through coupling capacitor C2. Detail specification limits for ZZT shall apply at 45 through 60 at frequencies greater than 60 Hz shall be corrected to those readings taken at 45 through 60 Hz. This current shall be 10 percentof the value of the dc breakdown current through the DUT. The small-signal impedance shall be determined as follows:4. Summary. Unless otherwise specified in the detail specification, the following conditions shall and ac test frequency, if other than 45 to 1,000 FORWARD IMPEDANCE1. Purpose. The purpose of this test is to measure the forward impedance of the device under small-signal Test circuit. See figure : 1. The impedances of C1 and C2 shall be small compared to the DUT at the test frequency. 2. Voltmeters VAC and V2 shall be high input impedance types. 3. The resistance of R1 shall be large compared with the forward impedance being measured. 4. A low pass filter may be installed in series with the ac signal 4056-1. Test circuit for small-signal forward Procedure. The specified forward direct current shall be applied to the DUT. An ac signal in the frequency range of 45 through1,000 Hz shall be applied to the DUT through coupling capacitor C2. Detail specification limits for Zf shall apply at 45 through 60 at frequencies greater than 60 Hz shall be corrected to those readings at 45 through 60 Hz. This current shall not be greater than10 percent of the value of the dc forward current If. The small-signal impedance shall be determined as follows:4. Summary. The following conditions shall be specified in the detail and ac test frequency, if other than 45 to 1,000 CHARGE1. Purpose. The purpose of this test is to measure directly the charge recovered from a semi-conductor diode when it is rapidlyswitched from a forward biased condition to a reverse biased Test circuit. See figure 4061-1FIGURE 4061-1. Test circuit for stored Test diode under test is forward biased by the current flowing from voltage source number 2 through diode D1 andthrough resistor R1 to voltage source number 1. The diode under test is periodically reverse biased by the pulsefrom the generator and the charge stored in the diode is caused to flow through diode D2 and is measured on thecurrent meter. A similar measurement is made at zero bias current to determine the component of chargeresulting from the diode capacitance and the stray circuit capacitance. The stored charge can then be computedfrom the current readings and the pulse R1 should be large enough to ensure a constant current through the diode under test. Capacitor C1 should be largeenough to maintain a nearly constant voltage across the diode under test during the pulse. The output impedance of the pulsegenerator including R3 should have a low value, preferably 10 to 25 :. The rise time of the pulse should be short enough andthe pulse length should be long enough so that further change will not alter the measurement D1 should have a much smaller stored charge than the diode under test. Diode D2 should have a fast turnon time, a low dynamic resistance at high currents, and a low reverse leakage current. Capacitors C2 and C4should have low inductance and should be of sufficient capacitance so that a further increase in their values wouldnot alter the measurement results. The current meter should be of sufficiently low impedance that the averagevoltage drop across it during any test does not exceed 10 millivolts. Capacitor C3 should be of sufficient size thata small current will flow through the current meter with the diode under test removed. Resistor R2 should haveapproximately the same value as the output impedance of the pulse of portion of the circuit within the dotted lines should be constructed in accordance with good practices for highspeed pulse circuits. Particular attention should be paid to minimizing the circuit inductance including theconnections to the diode under test. The capacitance between point A and ground should be made as small Test the pulse generator for the desired amplitude, pulse width, and frequency (f). Set voltage source one tozero. Insert the diode under test and adjust voltage source two for the specified voltage from point A to ground asmeasured on a high impedance voltmeter. A common value used for this voltage is volts. Read the current, I1, flowing through the current voltage source one for the specified forward current through the diode under test. Adjust voltage source twofor the specified voltage from point A to ground. This voltage must be the same as used in Read the current,I2, flowing through the current stored charge is given by:5. Summary. The following conditions shall be included in the detail bias current If at which the stored charge measurement is made (see 4.). generator rise time (1 percent to 50 percent), amplitude, width, impedance, and frequency (see 4.).METHOD CURRENT1. Purpose. The purpose of this test method is to subject the DUT to high current stress conditions to determine the ability of thedevice chip and contacts to withstand current Applicability. This test method describes two different approaches to applying high current stress conditions. Current is applied inthe forward direction to signal diodes and rectifier diodes, and in the reverse direction to voltage regulator (zener) diodes. The firstmethod uses half sinusoidal current surges, at low duty factor, applied to either a baseline ac or dc. It is intended primarily for lot sampleassurance tests. The second method uses rectangular current pulse(s) and is intended primarily for 100 percent screening of signaldiodes and where otherwise applicable. W hen used with zener diodes, primarily for lot sample assurance testing, this method utilizes amonitoring circuit to sense possible voltage collapse during the current specifically stated otherwise in the device specifications, the condition chosen shall be applicable to the particular device and testintent; high current devices may use condition Definitions. The following symbols and terms shall apply for the purpose of this test :Average ac forward current (in A). :DC forward current (in A). :DC reverse zener current (in mA). (surge):Peak value of surge current (in A). (surge):Peak value of zener surge current (in mA). (surge):DC surge current (in A). (surge):DC value of surge current (in mA). :Nonrepetitive maximum reverse voltage (in V). (wkg):Working maximum reverse voltage (in V). (surge):DC surge voltage (in V). (surge):DC surge voltage (in V). :Number of tp:Duration of current surge pulses (in ms). factor:Applied current surge pulses (in percent).METHOD of 5MIL-STD-750DFIGURE 4066-1. Surge pulse applied to continuous halfwave conditions (condition A1).FIGURE 4066-2. Surge pulse applied to continuous dc conditions (condition A2).METHOD Condition A, sinusoidal current Apparatus. (As required). Procedure. The continuously-applied electrical conditions shall be specified and applied to the device under the specifiedconditions. Unless otherwise specified, the specified number of current pulses (n) shall be superimposed on the continuously-appliedelectrical conditions at the specified duty factor in accordance with figure 4066-1 (condition A1) for rectifiers, or figure 4066-2, (conditionA2) for signal and switching diodes, zeners, bridges, as applicable. The surge pulses shall be half-sine waveform and of specifiedduration (tp). The duty factor shall be so chosen that the junction temperature is not changed Test conditions to be specified and recorded. The following conditions shall be specified in the detail forward current IO; or forward current (dc), IF or IZ for zener diodes; as of current pulses (n). of pulses (tp), normally cycle of pulses, normally less than one percent, or the period (normally between 6 and 60 seconds). value of current pulse (if(surge) or IZ(surge)), normally full rated or some effective (rms) current for maximum reverse voltage (VRSM), when after , lead, or ambient temperature (TC, TL, or TA), as Condition B, rectangular current Apparatus. The current source (I) and switch (SW ) combination shown on figure 4066-3 shall be able to apply the peak value ofcurrent pulse (IF(surge) or IZ(surge)) for the pulse duration (tp) as required in the transitions from off-to-on and from on-to-off in a timeperiod less than 10 percent of the pulse duration (tp) and shall be able to handle any number of pulses (n) and duty cycle as required inthe detail specification. For zeners the dashed lines replace the solid connecting lines (vertical) to the DUT. The monitor must becapable of sensing any collapsing zener voltage below rated VZ(min) during the full tp that IZ(surge) is applied. Any collapse, howevermomentary is considered a 4066-3. Rectangular current pulse test Procedure. As shown on figure 4066-4, no current is applied to the DUT prior to the starting time (to) of the test. For zeners, amaximum of 5 percent of rated IZ may be used. At to, SW causes the application of IF(surge) for time period tp, after which SW causesthe current to cease flowing in the DUT. For multiple pulse requirements, SW again causes current flow in the DUT after being off for atime necessary to meet the factor cycle requirements; this process is repeated for n times as specified. The duty factor and pulse width(tp) shall be chosen to ensure that the DUT junction temperature is not changed 4066-4. Rectangular current pulse Test conditions to be specified and recorded. The following conditions shall be specified in the detail value of current pulse (IF(surge)or IZ(surge) for zeners). This is normally the same RMS current as the rated half sinecondition for rectifiers. Zeners normally are specified with square wave dc value of surge of current pulses (n), suggest between 1 and of pulses (tp), suggest ms (to achieve same results as referenced in ). factor of pulses, normally less than one (min) to be monitored during IZ(surge) for after test (see ).METHOD Alternative to measurements after test (*). There is a minor modification to the test method that offers the advantage ofimmediately determining if the DUT survived the test. This consists of monitoring the forward voltage (VF(surge)) during tp to determineif device degradation, open-circuit or short-circuit conditions occur. A recorded value of VF(surge) can be compared to minimum andmaximum values in the detail specification to determine if the device survived the test. (*) NOTE: Zener monitoring is mandatory; it is notan alternative. Collapse below VZ(min) is a Condition C (with external heating). The worst case test condition for surge current is for device junction temperature at the ratedmaximum allowable junction temperature. Test condition A approximates this condition by applying forward current to dissipate power inthe DUT. The product of this power dissipation and the device thermal resistance produces a temperature rise of the junction over thecase temperature at which the surge test is performed. This represents what actually happens to a device in use. However, the actualjunction temperature during the surge current test is only at the rated allowable maximum for those individual devices which have both theworst case maximum forward voltage drop and the worst case maximum thermal impedance. Only a very small percentage of actualdevices will truly be worst case. The vast majority of devices will be tested at junction temperatures below rated condition C avoids this short fall in junction temperature and truly represents worst case operation by externally heating the DUT tothe specified rated maximum operating junction temperature of the DUT. Consequently there is no applied heating current prior to orconcurrent with the surge current. Once the DUT has stabilized at thermal equilibrium at the specified maximum operating junctiontemperature, the desired surge current pulses are applied at the specified duty cycle. The time between current surges must be longenough to permit the device junction temperature to return to its original thermal Summary. The following conditions shall be specified in the individual condition temperature, forward current, IO; forward current (dc), IF or zener current (dc), IZ; as applicable (IO = 0 for test conditions B andC). of current pulses (see 3.). of pulses (see 3.). factor of value of current pulse, if(surge) or iZ(surge) as reverse voltage (non-repetitive), VRSM. (VRSM = 0 for conditions A2 and C.) after COEFFICIENT OF BREAKDOWN VOLTAGE1. Purpose. The purpose of this test is to measure the temperature coefficient of breakdown voltage under specified Apparatus. The apparatus used to measure the temperature coefficient of breakdown voltage shall be capable of demonstratingdevice conformance to the minimum requirements of the individual Procedure. The temperature coefficient of breakdown voltage is the percent of the voltage change from the breakdown voltageobtained at the specified reference temperature to the breakdown voltage obtained at the specified test shall be calculated using the following formula: Where the reference temperature is the actual ambient (+25qC r3qC) and the test temperature is the extreme temperature employed inthe Summary. The following conditions shall be specified in the detail CURRENT1. Purpose. The purpose of this test is to measure the saturation current under the specified Test circuit. See figure 4076-1. Test circuit for saturation Procedure. The supply voltage is adjusted until the specified reverse voltage across the diode is achieved. The saturation currentis then read from the current meter. Unless otherwise specified, the reverse voltage for measurement of saturation current shall beapproximately 80 percent of the nominal breakdown voltage for voltage regulator diodes and approximately 80 percent of the minimumbreakdown voltage for Summary. The test voltage (see 3.) shall be specified in the detail specification:METHOD RESISTANCE OF LEAD MOUNTED DIODES(FORWARD VOLTAGE, SWITCHING METHOD)1. Purpose. The purpose of this test is to determine the thermal resistance of lead mounted diodes under the specified Definitions. The following symbols shall apply for the purpose of this test :Thermal resistance, junction-to-reference point, in degrees :Junction temperature in degrees :Reference point temperature in degrees :Magnitude of heating power in watts applied to diode causing temperature difference TJ - :Magnitude of power in watts applied to diode during measuring and :Measuring current in :Value of temperature-sensitive parameter in millivolts, measured at IM, and corresponding to the temperature of thejunction heated by :Calibration temperature in degrees Celsius, measured at reference :Value of temperature-sensitive parameter in millivolts, measured at IM and specific value of :Lead temperature in degrees Celsius, measured at the reference point prior to application of heating power :Lead temperature in degrees Celsius, measured at the reference point after the junction has been heated by :Heating power duty Apparatus. The apparatus required for this test shall include the following as applicable to the specified test material shall be copper-constantan (type T) or equivalent, for the temperature range -180qC to +370qC. Thewire size shall be no larger that AWG size 30. The junction of the thermocouple shall be welded to form a bead rather thansoldered or twisted. The accuracy of the thermocouple and associated measuring system shall be temperature chamber or heat sink capable of maintaining the specified reference point temperature to within the preset (measured) electrical equipment as required to provide controlled levels of conditioning power and to make the specifiedmeasurements. The instrument used to electrically measure the temperature-sensitive parameter shall be capable ofresolving a voltage change of mV. An appropriate sample-and-hold unit or a cathode ray oscilloscope shall be used forthis of 4MIL-STD-750D3. Procedure. In measuring thermal resistance, the forward voltage is used as the temperature-sensitive parameter (TSP) to indicatethe junction temperature (see figure 4081-2 for mounting arrangement). application test. The power application test shall be performed in two parts. For both portions of the test, the referencepoint temperature shall be held constant at the specified value. The value of the temperature-sensitive parameter VMC shallbe measured with a measuring current (IM) which will produce negligible internal heating. The diode under test shall then beoperated with heating power (PH) intermittently applied at a greater than or equal to 98 percent duty factor. Thetemperature-sensitive parameter VMH shall be measured during the interval between heating pulses (d 300 Ps) with constantmeasuring current (IM) applied. If, as can be the case with axial devices, it is not possible to maintain the lead temperatureconstant during the power application test, the difference in the lead temperature at which VMH and VMC are measured shallbe recorded. This lead temperature difference (TLH - TLC) divided by the average heating power (DPH) shall be subtractedfrom the calculated thermal resistance to correct for this error. It is not possible, due to the presence of electrical transients inthe voltage waveform, to measure the TSP at the instant that the heating current is removed. For a particular device type theshortest time after removal of heating current that the TSP shall be measured is found by performing the test at various powerlevels and noting the shortest time where the measured value of thermal resistance is essentially independent of powerdissipated. Power levels of 25 percent above and below the power corresponding to the specified heating current arerecommended for determining this delay time. The junction-to-lead thermal resistance shall therefore be calculated from thevalue of the temperature-sensitive parameter VMH as measured at the previously determined delay time (usually between 10and 50 Ps). If, as can be the case with axial lead devices, it is not possible to maintain the lead temperature constant duringthe power application test, the difference in the lead temperature at which VMH and VMC are measured shall be lead temperature difference (TLH - TLC) divided by the average heating power (DPH) shall be subtracted from thecalculated thermal resistance to correct for this error. The heating power (PH) shall be chosen such that the calculatedjunction-to-reference point temperature difference as measured at VMH is greater than or equal to + of the temperature coefficient of the temperature-sensitive parameter (calibration). The temperature coefficientof the temperature-sensitive parameter shall be measured utilizing the chosen measuring current (IM) used during the PowerApplication Test. The DUT shall be externally heated in an oven or on a temperature controlled heat sink. The measuringcurrent shall be chosen such that the temperature-sensitive parameter varies linearly with temperature over the range ofinterest and that negligible internal heating (PC | 0) occurs during the calibration procedure, , TR | TJ. The referencepoint temperature range used during calibration shall encompass the temperature range encountered in the Power ApplicationTest. The value of the temperature-sensitive parameter temperature coefficient ('VMC/'TMC) shall be calculated from thecalibration curve (VMC versus TMC). It can generally be assumed that, for devices of a given design and construction, thetemperature coefficient of the temperature-sensitive parameter is constant. The temperature coefficient shall be measured on10 devices to validate this assumption. If the relative sample standard deviation of these measurements is less than or equalto r3 percent, the average of the measured temperature coefficients can be used in the calculation of thermal resistance for allother devices of the design and Calculation of thermal resistance. For axial lead diodes the reference point for calculations of the junction-to-lead thermalresistance (RTJL) shall be at a point on the lead .375 inch ( mm) from the body of the diode under test. For thermally unsymmetricaldevices, the specified lead temperature shall be the average of the two lead temperatures measured with both leads terminated thermallyin the same manner. The following equation is used to calculate the junction-to-lead thermal resistance: where VMC is the value of the temperature-sensitive parameter for TMC equal to TLC and TLH - TLC corrects for variations in the leadtemperature during the Power Application Test. Measurements of TR and TMC are made by means of a thermocouple attached to thereferenced point. The power dissipation in the DUT is calculated from the equation PH = IVVF. If the power dissipation duringmeasuring and calibration is not negligible, then PC should be subtracted from PH when calculating the thermal resistance. Thespecimen junction-temperature shall be considered stabilized when halving the time between the initial application of power and the takingof the reading causes no error in the indicated results within the required accuracy of Test circuit. See figure 4081-1. Test circuit is controlled by a clock pulse with a pulse width less than or equal to 300 Ps and repetition rate less than or equal to When the voltage level of the clock pulse is zero, the transistor Q1 is off and the forward current through the DUT is the sum of theconstant heating current and the constant measuring current. Biasing transistor Q1 on, shunts the heating current to ground andeffectively reverse biases the diode D1. The sample-and-hold unit (S and H) (or cathode ray oscilloscope) is triggered when the heatingcurrent is removed and is used to monitor the forward voltage of the diode under test. During calibration, switch S1 is Summary. The following conditions shall be specified in the detail point temperature for heating power or reject 4081-2. Mounting SeriesElectrical characteristics tests for microwave diodes1. Measurement of conversion loss, output-noise ratio, and other microwave parameters shall be conducted with the devicefitted in the holder. All fixed adjustments of the holder shall be made at a laboratory designated by the Government. In the testequipment, the impedance presented to the mixer by the local oscillator (and the signal generator, if used) shall be thecharacteristic impedance of the transmission line between the local oscillator and mixer (the maximum VSWR, looking toward thelocal oscillator, shall be at the signal and image frequencies).2. For qualification inspection of reversible UHF and microwave devices, the radio-frequency measurements, excluding thepost-environmental-test end points and high-temperature-life (nonoperating) end points, shall be made, first, with the adapter onone end of the device, and then repeated with the adapter at the opposite end of the device; for the environmental and life tests,fifty percent of each sample shall be tested with the adapter on one end of the device and the remaining half of the sample shallbe tested with the adapter on the opposite end of the device. End-point measurements shall be made without moving theadapter. This procedure shall be repeated on at least one lot every 6 For quality conformance inspection of reversible UHF and microwave devices, the electrical measurements, including thepost-environmental-test end points, may be made with the adapter on either end of the LOSS1. Purpose. The purpose of this test is to determine the ratio of the available RF input power to the available IF output power underspecified Test circuits. The following test circuits shall apply:FIGURE 4101-1. Test setup for incremental 4101-2. Output circuit for the incremental 4101-3. Test setup for heterodyne of 4MIL-STD-750DFIGURE 4101-4. Test setup for modulation Overall noise figure method. See method 4121 for output noise ratio and method 4126 for overall noise Test condition A (incremental). The equipment for this test is shown in figures 4101-1 and 4101-2. An expression for conversionloss is shown in the equation:L = Conversion loss.'I = Incremental change in current.'P = Incremental change in = Average power (P + 'P). 1Gb = Zm'I---- = IF conductance of diode under test. 'V 1IF conductance = ZifThe diode is loaded by the resistance RL + r2 that is adjusted to the specified load impedance (Zm). ZmRL is the dc load resistance;load resistance shall be specified. The current supplied by the battery balances out the diode current at some standard power level P,and makes the current in the microammeter zero. With a change in power 'P, 'I can be measured directly. With the injection of a smallvoltage (few millivolts) 'V at Po power level, 'I can be directly measured. (This impedance can be measured by other means. See IFimpedance, method 4116, Zif.) These values can be inserted in the equation and the conversion loss can be calculated for the conditionsof Test condition B (heterodyne). A signal generator feeds signal power to the mixer that converts the power to the IF by beating withthe local oscillator. The converted power is measured with an IF power meter. Both the available signal power from the generator at A,shown on figure 4101-3 and the increase in the available IF power at B shall be measured when the noise is applied, their ratio being theconversion Test condition C (modulation). The equipment for this test is shown in figure 4101-4. Conversion loss is given by the equation: m = modulation = available = rms modulation voltage across = ratio of load conductance to IF = 1 ZmTo avoid measuring Gb for each unit, the factor 4n is assumed to be unity. (1 + n)2The error caused by this approximation is less than dB and is in such a direction to make a unit with an extreme conductance the modulation coefficient is difficult to measure, this equipment is calibrated with standard diodes measured by any high impedance voltmeter can be used to measure 20 log EB directly. The voltmeter is set on the volt full scale, and themodulation voltage set so that the term 10 log(m2p/Gp) is equal to on the dB scale. To obtain this setting, the modulation isadjusted, so the voltmeter reading on the decibel scale is minus the value of conversion loss for the standard diodes. Thiscorresponds to a value of m of percent for P = mW and Gp = .0025 :. The conversion loss for unknown diodes is then the reading of the output meter in Test condition D (overall-noise-figure). The overall-noise-figure method derives the conversion loss by known properties of theapparatus and is expressed by the equation: _ Fo = L(N + Fi -1) Where:L = conversion loss of the = output noise ratio of the = noise figure of the IF is measured as described in method 4101 and N is measured as described in method terms are Detail drawings. The following drawings, as applicable, are used in the performance of this test: JAN 103, 107, 124, 174, 233,234, and 266; DESC D64100, C64169, D65019, C65042, D65084, C65101, C65017 and Summary. The following conditions shall be specified in the detail condition (see 3.). impedance (Zm) (see ). oscillator power (see ). resistance (RL) (see ). oscillator frequency (see ).METHOD 4102MICROWAVE DIODE CAPACITANCE1. Purpose. The purpose of this test is to measure the low frequency capacitance of a semiconductor diode. The capacitance is thesmall signal capacitance of the diode as measured in a defined test holder under specified bias Test circuit. A bridge or meter should be used for the measurement. The specified signal level at the diode terminals, as measuredwith a suitable voltmeter, should be low enough so that a doubling of the level produces no measurable change in either the capacitanceor shunt conductance of the diode. The test holder should be constructed so that the fringing capacitance is not altered by inserting Procedure. The measurement shall be made at a specified frequency and bias voltage. A low frequency capacitance bridge ormeter is used to measure the capacitance of the diode at a specified bias point. The effective case capacitance is measured in the sametest holder as the diode. Junction capacitance may be determined by subtracting the effective case capacitance from the total Summary. The following conditions shall be specified in the detail (see 3.). voltage (see 3.). level at diode terminals (see 2.). point (see 3.).METHOD 41021/2MIL-STD-750DMETHOD 4106DETECTOR POWER EFFICIENCY1. Purpose. The purpose of this test is to measure the detector power Test circuit. See figure 4106-1. Test circuit for detector power Procedure. Resistor RL and capacitor C1 comprise the load circuit and shall be as specified. Resistor R1, in conjunction with RL,provides the specified bias current for the DUT. Capacitor C2 provides RF bypass for the output current meter IDC. The frequency andamplitude of the ac signal and the output impedance of the generator shall be as specified. The change in output current Idc is measuredwhen the ac signal is applied. 4. Summary. The following conditions shall be specified in the detail for circuit components RL and C1 (see 3.). current (see 2.). and amplitude of ac signal (see 3.). of signal generator (see 3.).METHOD 41061/2MIL-STD-750DMETHOD OF MERIT (CURRENT SENSITIVITY)1. Purpose. The purpose of this test is to measure the figure of merit of a semiconductor detector diode. The figure of merit is asfollows: 2. Test circuit. The following test circuit shall apply:NOTE: For power 4111-1. Test setup for figure of merit of 3MIL-STD-750D3. Procedure. The equipment for this test is shown in figure 4111-1. A continuous wave (cw) radio frequency (rf) signal is applied tothe detector whose output short circuit current is measured and the short circuit current sensitivity ( ) is computed. The figure of merit(M) is then determined from: Approximate method: Where: = i/Pandi = short circuit diode currentP = power incident at the diode holderWhere:andR1 = lower limit of video resistanceR2 = upper limit of video resistanceRa = equivalent amplifier noise generating where: and: When the extreme values of the video resistance for a given diode type are known, it is possible to relate figure of merit to rectified currentif other conditions are all normal ranges of video resistance, the correction factor is very close to unity and an approximation: therefore, the figure of merit (M) may be determined by measuring the rectified current under proper Summary. The following conditions shall be specified in the detail oscillator frequency (see 2.). permissible test oscillator power (see 2.). bias if supplied by an external , if other than 1,200 :.METHOD IMPEDANCE1. Purpose. The purpose of this test is to measure the real part of the impedance at the IF output terminals of the mixer diode Test circuit. The following test circuits shall apply:FIGURE 4116-1. AC 4116-2. Impedance bridge Procedure. Since the IF resistance is the slope of the mixer diode's I-V characteristic under the specified test conditions, therequirement of any measuring technique is to measure the slope without affecting the operating characteristics of the DUT. At all times,the device holder RF input port should see a broadband match (minimum of two times IF frequency). The IF test frequency, localoscillator frequency, and power shall be Test condition A (ac). With equipment arranged as shown in figure 4116-1, a constant current ac generator is coupled to thediode under test. The dc and ac diode loads are arranged as specified and the ac current is set at a level low enough so that halving thelevel produces a change in the measured IF impedance of the diode of less than 5 percent. The IF impedance is calculated as follows:Where: Zif = diode IF impedance. V = measured ac voltage. I = ac of Test condition B (impedance bridge). The equipment is arranged as shown in figure 4116-2. The impedance bridge signal level isadjusted to a low level using the same criterion in The diode IF impedance is determined from the impedance Detail drawings. The following drawings, as applicable, are used in the performance of this test: JAN 107, 124, 174, 233, 234, and266; DESC D64100, C64169, D65019, C65042, D65084, C65101, C65017 and Summary. The following conditions shall be specified in the detail condition (see 3.). oscillator frequency (see 3.). oscillator power or diode rectified current (see 3.). load resistance (see and ). load impedance (see and ). test frequency (see 3.). bias, if NOISE RATIO1. Purpose. The purpose of this test is to measure the output noise ratio of a mixer diode. Since the output noiseratio is a measure of the excess noise generated by a mixer diode in its normal operating condition, the measurementshould be in the appropriate standard Test circuit. The following test circuits shall apply:FIGURE 4121-1. Direct measurement 4121-2. Y-factor Test condition A (direct measurement). In this method the output noise ratio is determined by establishing areference output reading on the output meter shown in figure 4121-1, with the diode operating under specified testconditions, then a resistor equal to the specified IF impedance of the diode is substituted for the diode. The resistorbecomes noisy when the current passes from a noise diode (temperature limited diode). Value for noise resistor shallbe specified. The current is adjusted to provide the reference output reading and the noise ratio is computed from therelationship:Where: To = +293qK r5qK and I is the current of the noise diode in amperes. R = the resistance of the noise resistor. k = Boltzmann's constant ( x 10-23 joules per qK). e = the electronic charge ( x 10-19 coulombs).METHOD of Test condition B (computational). In this method the output noise ratio is determined from the equation: _ Fo _ N = L - Fi + 1Where: _ Fo = overall receiver noise figure. L = diode conversion loss. _ Fi = noise figure of the IF amplifier. All terms are ratios. _Fo and Fi are determined as described in method 4126; L is determined as described in method Test condition C (Y-factor). In this method the output noise ratio is determined by establishing a referenceoutput reading on the output meter shown in figure 4121-2, with the diode operating under specified test conditions,then a resistor equal to the specified IF impedance of the diode is substituted for the diode by a switch in the Y-factorcircuit. The output noise ratio is then determined from: _ N = Fi (Y -1) + 1where: Y = Noc/Nor Noc is the reference output reading on the output meter with the diode connected to the circuit. Nor is the output reading with the resistor connected to the circuit. _ Fi is determined as described in method 4126. All terms are Detail drawings. The following drawings, as applicable, are used in the performance of this test: JAN 103, 107,124, 174, 233, 234, and 266; DESC D64100, C64169, D65019, C65042, D65084, C65101, C65017 and Summary. The following conditions shall be specified in the detail condition (see 3.). oscillator frequency (see 2.). oscillator power (see 2.). frequency (see 2.). for noise resistor (see ). bias, if NOISE FIGURE AND NOISE FIGURE OF THE IF AMPLIFIER1. Purpose. The purpose of this test is to measure the overall noise figure of a mixer diode and the noise figure of the associated IFamplifier. Since the noise figure of a network is defined as follows: (available input signal power)/(available input noise power) Fo = -------------------------------------------------------------------------------- (available output signal power)/(available output noise power),it is necessary to measure the noise power that is actually delivered to the output termination. This measurement is divided by a similarmeasure of the output noise that would have been obtained if the network were noiseless and only transmitted the thermal noise of theinput termination. In making noise figure measurements, the standard practice is to provide matched impedance at the signal and imagefrequencies and make suitable corrections (by calculations or appropriate filtering) to obtain an equivalent single-side-band noise noise figure obtained without a signal band-pass filter to eliminate the image-frequency band is commonly referred to as thedouble-side-band noise figure and is approximately 3 dB smaller than the single-side-band noise figure, depending on the exacttransmission characteristics of the particular mixer. If a single-side-band noise figure is being measured directly, it is necessary toterminate the image resistively in a matched load (isolator) to avoid errors due to second-order effects. These second-order effects mayarise from reflection of the image back into the mixer to give a larger- or smaller-than-true value of noise figure, depending on the phase ofthe reflected Apparatus. The apparatus shall be arranged as follows:FIGURE 4126-1. Test setup for overall noise Procedure. When using test methods A and C the local oscillator frequency and power, IF, and excess noise ratio of noise sourceshall be Test condition A (dispersed-signal-source). A signal source with available power dispersed uniformly over the pass band of thenetwork, and calibrated in terms of available power per unit bandwidth is used to determine that portion of the output noise power thatresults from the input termination noise. Suitable dispersed-signal generators are thermionic-noise diodes, gas- discharge tubes,resistors of known temperature or an oscillator whose frequency is swept through the band at a uniform rate. Single-side-band noisefigure is obtained by adding 3 dB to the measured (double-side-band) noise figure. At all times the device holder rf input should see abroadband match (minimum of two times IF frequency).METHOD of Test condition B (computation). Assuming the IF amplifier noise figure is known, the overall noise figure can be computed asfollows: _ _Fo = L (N + Fi -1)Where:L = diode conversion = output noise ratio of the diode. _Fi = noise figure of the IF is measured as described in method 4101 and N is measured as described in method terms are Test condition C (IF amplifier noise figure). Resistors in the particular diode type cases are required, constructed so that whenthey are inserted in the standard holder (mixer), the output susceptance of the holder is approximately the same as when the diodes areinserted. A sufficient number of resistors should be used so that the output conductance of the standard holder may be finely varied overthe specified maximum range for the diode type. A common junction (defining the mixer IF port) joins the holder to the IF amplifier andthe noise (temperature-limited diode). The entire circuit, including the noise diode power supply and the current meters, must be wellshielded or filtered to avoid IF feedback. With the resistor in the holder, the IF amplifier gain is adjusted to give an output meter referencereading near full scale. Precise IF attenuation is then inserted, and the noise diode turned on and adjusted in emission to restore theoutput meter reference reading. The average (dc) noise anode current is then noted and used to compute the IF average noise figurefrom:Where:Fi = noise figure of the IF amplifier (power ratio).e = electronic charge ( x 10-19 coulombs).k = Boltzmann's constant ( x 10-23 joules per qK).To = standard noise temperature (+293qK).Ta = temperature of resistor (qK).A = inserted IF attenuation (power ratio).I = average (dc) noise diode current (amperes).R = reciprocal of IF conductance (ohms).METHOD Summary. The following conditions shall be specified in the detail condition (see 3.). oscillator frequency (see 3.). oscillator power (see 3.). (see 3.). bias, if bias is supplied by an external noise ratio of noise source (see 3.).METHOD RESISTANCE1. Purpose. The purpose of this test is to measure the video resistance of the device. Video resistance shall be defined as thereciprocal of the slope of the current versus voltage characteristic curve at the operating Test circuits. The test circuits shall be as follows:FIGURE 4131-1. Constant voltage 4131-2. Constant current 4131-3. Pulsed RF of 2MIL-STD-750DFIGURE 4131-4. Continuous wave RF Procedure. The measurement shall be made with the diode operating under the specified test conditions. The applied signal usedand the instrument impedance shall be such that doubling or halving their value does not change the video impedance by more than Test condition A (constant voltage). Test equipment used is shown in figure 4131-1. A small specified ac signal is applied to thediode from a constant voltage source. Current is measured with a low resistance microammeter. RV equals Test condition B (constant current). Test equipment used is shown in figure 4131-2. A small specified ac current is passedthrough the diode from a constant current source. The voltage is measured across the device with a high impedance millivoltmeter. RVequals Test condition C (pulsed rf). Test equipment used is shown in figure 4131-3. A pulsed rf signal, as specified, is fed to the diodewhose output is fed into the vertical amplifier of an oscilloscope. A resistor is placed in parallel with the device and varied to lower therectified pulse to half its value. RV equals the resistance required to halve the pulse. Bandwidth of vertical amplifier should be aminimum of two times the reciprocal of the pulse Test condition D (continuous wave (cw) radio frequency (rf)). Test equipment used is shown on figure 4131-4. A specified cw rfsignal is applied to the detector whose output open circuit rectified voltage is measured on a high impedance dc millivoltmeter. A resistoris placed in parallel with the device and varied to lower this voltage to half its initial value. RV equals the resistance required to halve Summary. The following conditions shall be included in the detail condition (see 3.). signal voltage (see ). current (see ). power (see and ). bias, if WAVE RATIO (SWR)1. Purpose. The purpose of this test is to measure the SWR of the device at the local oscillator terminals. SWR shall be defined asthe ratio of the maximum voltage (or current) to the minimum voltage (or current) along the transmission line between the device and thelocal oscillator terminals. The measurement shall be made with the diode operating under normal operating Test circuits. The test circuits shall be as follows:FIGURE 4136-1. Slotted line 4136-2. Reflectometer of 2MIL-STD-750D3. Test condition A (slotted line). A slotted line is inserted between the device in its holder and the local oscillator, and the probe ismoved to determine the maximum and minimum voltage or current points. To limit probe errors and keep the power in the slotted linesection at a level high enough to operate the standing wave indicator and low enough to maintain small signal conditions, the normalsignal generator and indicator connections to the slotted as shown in figure 4136-1 should be interchanged. That is, the signal generatorshould be connected to the moving probe and the detector indicator should be connected to the slotted line section opposite the test power source may be used without modulation if a sensitive galvanometer is substituted for the standing wave indicator(tuned voltmeter). dc load resistance is set to that diode into test frequency and power level to those the probe in the slotted line until the standing wave indicator shows at voltage maximum (or current). Adjust the rangeswitch and gain until an SWR of 1 is the probe until a minimum is the SWR directly at the minimum Test condition B (reflectometer). A calibrated reflectometer is inserted between the device in its holder and the local oscillator;then the SWR is read, see figure frequency and power level to those dc load resistance is set to that diode into the test reflection coefficient and the SWR can be read : When this technique is used, the filter detector combination shall have an SWR < Summary. The following conditions shall be included in the detail condition (see 3.). load resistance (see and ). frequency (see and ). level (see and ). voltage (or current), if BY REPETITIVE PULSING1. Purpose. The purpose of this test is to determine the capabilities of the device to withstand repetitive Test circuit. See figure 4141-1. Test setup for repetitive Procedure. This method shall be acceptable to determine the device capability to withstand repetitive pulses. The general methodof measuring device capability to withstand burn-out by repetitive pulsing is to apply the specified number of pulses to the DUT and thenmeasure the specified electrical parameters. The pulse polarity shall be such as to cause the current to flow in the forward the maximum change in the specified electrical parameter is exceeded, the device shall have failed to meet this burnout test. Thepulse generator source impedance shall be specified. While the device to be tested is not in the circuit, adjust the pulse generator outputfor the specified open-circuit pulse voltage, pulse width, and pulse repetition rate. Then insert the device in the circuit. The device shallbe left in the circuit for a minimum specified Summary. The following conditions shall be specified in the detail generator source impedance (see 3.). width (see 3.). voltage (see 3.). repetition rate (see 3.). time that the device is under test (see 3.). of applied pulse (see 3.). pulse energy per pulse absorbed by diode, if BY SINGLE PULSE1. Purpose. The purpose of this test is to determine the capability of the device to withstand a single Test circuit. The test circuit shall be as follows:FIGURE 4146-1. Burnout by single Procedure. The device shall be subjected to a pulse from the coaxial line shown in figure 4146-1. The line shall be charged withthe specified voltage, and the contact shall be made by dropping the center conductor vertically from a height of 2 inches ( ) above the contact position. The electrical and mechanical connection shall be such as to have a minimum effect on the free fall ofthe conductor. The polarity of the inner conductor with respect to the outer conductor shall be such as to cause the device current to flowin the forward direction or as Detail drawing. DESC drawings B66054 and C66058 as applicable, are used to perform this Summary. The following conditions shall be specified in the detail voltage (see 3.). , if 4151RECTIFIED MICROWAVE DIODE CURRENT1. Purpose. The purpose of this test is to measure the rectified microwave diode current under conditions for conversion Apparatus. The apparatus used for this test should be capable of demonstrating device conformance to the minimum requirementsof the individual Procedure. The rectified microwave diode current shall be measured under the conditions for conversion loss. The test shall beconducted in the mixer shown on the specified drawing under the conditions specified for the conversion loss Summary. The following conditions shall be specified in the detail apparatus (see 2.). loss test conditions (see 3.).METHOD 41511/2MIL-STD-750D4200 SeriesElectrical characteristics tests for thyristors (controlled rectifiers)MIL-STD-750DMETHOD CURRENT1. Purpose. The purpose of this test is to measure the holding current of the device under the specified Test circuit. See figure 4201-1. Test circuit for holding Procedure. The anode supply voltage is set at its specified value with resistance R1 adjusted so that the initial forward current, IF1,which flows when the device is triggered equals the value specified. Switch SW is then momentarily closed to trigger the device andreopened. The initial current is quickly reduced to the specified test current IF2. Then the specified gate bias condition is applied. Theresistance R1 is then gradually increased, until the device turns off. The value of forward current immediately prior to turn-off is theholding Summary. The following conditions shall be specified in the detail supply voltage, forward current, test current, condition, gate to cathode, as applicable:A: Bias (specify VGG, gate-to-cathode polarity, equivalent bias circuit resistance, Re).B: Resistance return (specify value of R3).C: Short : Open trigger source voltage, open circuit magnitude and pulse gate trigger circuit resistance, BLOCKING CURRENT1. Purpose. The purpose of this test is to measure the forward blocking current under the specified conditions, using the dc methodor the ac method, as DC Test circuit. R1 shall be chosen to limit the current flow in the event the device switches to the "on" :The ammeter shall present essentially a short circuit to the terminals between which the current is being measured orthe voltmeter readings shall be corrected for the drop across the 4206-1. Test circuit for forward blocking current (dc method). Procedure. The supply voltage is adjusted to obtain the specified value of forward voltage across the device with the specifiedgate bias condition applied (see figure 4206-1). The forward blocking current is then read from the current Summary. The following conditions shall be specified in the detail condition, gate-to-cathode, as applicable:A: Bias (specify VGG, gate-to-cathode polarity, equivalent bias circuit resistance, Re).B: Resistance return (specify value of R2).C: Short : Open of 2MIL-STD-750D3. AC Test circuit. R1 shall be chosen to limit the current flow in the event the device switches to the "on" state. D1 and D2 are diodescapable of blocking the peak value of the ac voltage supply. Peak reading techniques shall be used to measure the necessaryparameters. NOTE:The ammeter shall present essentially a short circuit to the terminals between which the current is being measured orthe voltmeter readings shall be corrected for the drop across the 4206-2. Test circuit for forward blocking current, (ac method). Procedure. The peak supply voltage is adjusted to obtain the specified peak forward voltage across the device with the specifiedgate bias condition applied (see figure 4206-2). The peak forward blocking current is then read from the current indicator. Voltageshould be gradually applied to prevent turn-on of the device due to excessive Summary. The following conditions shall be specified in the detail forward test condition, gate-to-cathode, as applicable:A: Bias (specify VGG, gate-to-cathode polarity, equivalent bias circuit resistance, Re).B: Resistance return (specify value of R2).C: Short : Open BLOCKING CURRENT1. Purpose. The purpose of this test is to measure the reverse blocking current under the specified conditions, using the dc methodor the ac method, as DC Test circuit. R1 shall be chosen to limit the current flow in the event of the device goes into reverse breakdown. NOTE:The ammeter shall present essentially a short circuit to the terminals between which the current is being measured orthe readings shall be corrected for the drop across the 4211-1. Test circuit for reverse blocking current (dc method). Procedure. The supply voltage is adjusted to obtain the specified value of reverse voltage across the device with the specified gatebias condition applied (see figure 4211-1). The reverse blocking current is then read from the current Summary. The following conditions shall be specified in the detail condition, gate-to-cathode, as applicable:A: Bias (specify VGG, gate-to-cathode polarity, equivalent bias circuit resistance, Re).B: Resistance return (specify value of R2).C: Short : Open of 2MIL-STD-750D3. AC Test circuit. R1 shall be chosen to limit the current flow in the event the device goes into reverse breakdown. D1 and D2 arediodes capable of blocking the peak value of the ac voltage supply. Peak reading techniques shall be used to measure the necessaryparameters. NOTE:The ammeter shall present essentially a short circuit to the terminals between which the current is being measured orthe voltmeter readings shall be corrected for the drop across the 4211-2. Test circuit for reverse blocking current (ac method). Procedure. The peak supply voltage is adjusted to obtain the specified peak reverse voltage across the device with the specifiedgate bias condition applied (see figure 4211-2). The peak reverse blocking current is then read from the current Summary. The following conditions shall be specified in the detail reverse test condition, gate-to-cathode, as applicable:A: Bias (specify VGG, gate-to-cathode polarity, equivalent bias circuit resistance, Re).B: Resistance return (specify value of R2).C: Short : Open 4216PULSE RESPONSE1. Purpose. The purpose of this test is to measure the pulse response of the device under the specified Test circuit. See figure 4216-1. Test circuit for pulse Procedure. The pulse response of the device shall be measured in the circuit of figure 4216-1. R2 is adjusted to permit thespecified value of forward current to flow in the device being measured when it is the on state. C, R1, and the secured controlled rectifier,D2 are used to switch off the device being measured. C shall be large enough to ensure that the device will turn off. R1 limits therecurrent peak reverse current to below the rated value. The pulse repetition rate should be low enough to ensure that the anode-cathodevoltage of the device being measured reaches the value of forward working voltage specified for the Summary. The following conditions shall be specified in the detail voltage (see 3.). R2 (see 3.). 42161/2MIL-STD-750DMETHOD 4219REVERSE GATE CURRENT1. Purpose. The purpose of this test is to measure the dc reverse gate current of the device at a specified reverse gate Test circuit. R is chosen to limit the current in the event the reverse gate breakdown voltage is exceeded. NOTE:The ammeter shall present essentially a short circuit to the terminals between which the current is being measured orthe voltmeter readings shall be corrected for the drop across the 4219-1. Test circuit for reverse gate Procedure. Set the specified reverse gate voltage and read the reverse gate Summary. The dc reverse gate voltage shall be specified in the detail specification:METHOD 42191/2MIL-STD-750DMETHOD VOLTAGEORGATE-TRIGGER CURRENT1. Purpose. The purpose of this test is to measure the dc gate-trigger voltage or dc gate-trigger Test circuit. Care should be taken to minimize noise or spurious signals in the trigger :The ammeter shall present essentially a short circuit to the terminals between which the current is being measured or thevoltmeter readings shall be corrected for the drop across the 4221-1. Test circuit for gate-trigger voltage or gate-trigger Procedure. The anode voltage, V2, is set to the specified value. The gate voltage, V1, is slowly increased from zero. Thegate-trigger current or gate-trigger voltage is read as the highest value achieved prior to a sharp decrease in anode Summary. The following conditions shall be specified in the detail voltage, V2 (see 3.). resistance, gate circuit resistance, Re (the resistance looking into the gate circuit from the DUT gate-to-cathode terminals).METHOD 4223GATE-CONTROLLED TURN-ON TIME1. Purpose. The purpose of this test is to measure the time between initiation (10 percentage point) of gate pulse and the time atwhich the output pulse is at 90 percent of its final Test circuit. The anode circuit loop L/R shall be > and < of the forward current rise time, tr. The open-circuit, gate-voltagerise time shall be < of the delay time, td of the DUT. VAA must have stabilized at its peak value prior to triggering the gate 4223-1. Test circuit for gate-controlled turn-on 4223-2. Waveforms, gate-controlled turn-on 42231 of 2MIL-STD-750D3. Procedure. Set the anode voltage pulse source and the gate conditions as specified. Adjust RL to achieve the specified iFM. Theturn-on time is then read from the dual trace scope as shown on figure Summary. The following conditions shall be specified in the detail anode supply voltage, forward current, open-circuit, gate supply voltage, pulse width, gate source resistance, and maximum allowable di/dt of the forward current 42232MIL-STD-750DMETHOD 4224CIRCUIT-COMMUTATED TURN-OFF TIME1. Purpose. The purpose of this test is to measure the turn-off time of the device under the specified Test 4224-1. Circuit-commutated turn-off time 4224-2. Test circuit for circuit-commutated turn-off time. NOTE:The simplified circuit diagram on figure 4224-2 illustrates the operating principles of a circuit used to generate thewaveforms illustrated on figure 4224-1. For purposes of clarity, the circuit diagram utilizes current generators, idealswitches, and no provision for repetitive test 42241 of 2MIL-STD-750D3. Test description. The test is performed by first causing the thyristor under test to conduct the specified on-state current at thespecified thermal condition. This current is conducted for the specified time (a period long enough to establish carrier equilibrium). Next,the current is reversed through the thyristor at the specified rate (di/dt) by means of an externally applied reverse blocking voltage. Thereverse current recovers stored charge from the anode and cathode junctions of the thyristor, allowing the thyristor to support thespecified reverse blocking voltage. A further waiting time is required for the collector junction charges to recombine before the thyristor iscapable of blocking forward voltage. Since this recombination cannot be observed directly, the test is performed by applying an off-statevoltage at the specified rate of rise (dv/dt) after successively shorter waiting times until it is observed that the thyristor is unable to supportthe off-state voltage (without switching to the on-state). The thyristor current and voltage waveforms are illustrated on figure and S4 are closed simultaneously causing the thyristor under test to switch to the on-state and conduct thespecified current iFM; S4 is then opened to disconnect the gate trigger supply R1 and the specified on-state current duration, S3 is closed to cause current reversal. The rate of current change(di/dt) is determined by L1 and R2. Diode D2 prevents a commutation voltage transient when the thyristor undertest begins to recover its reverse blocking capability. Diode D1 must have a longer reverse recovery time than thethyristor under test so that the reverse voltage appears across the thyristor under application of off-state voltage is initiated by closing S1. The current I1 completes the reverse recovery of D1and is then diverted to C1. C1 charges linearly with time at a rate equal to I1/C1 producing the required dv/dtillustrated on figure 4224-1. This voltage rises to a value equal to V1 which is adjusted to the specified Summary. The following conditions shall be specified in the detail current current duration, rate (di/dt) (the slope of the line from 50 percent of + peak to 50 percent of - peak). reverse voltage (maximum). voltage at t1 (minimum). repetition of rise of reapplied off-state voltage (dv/dt). bias conditions (between gate trigger pulses):(1)Gate source voltage.(2)Gate source 42242MIL-STD-750DMETHOD 4225GATE-CONTROLLED TURN-OFF TIME1. Purpose. The purpose of this test is to measure the gate-controlled turn-off time of the device under the specified Test circuit. The circuit used for the test is shown on figure 4225-1. The thyristor is turned on by the gate pulse delivered by the"on pulse" generator. On-state current is determined by the off-state supply voltage and the load resistor a predetermined time a specified gate turn-off current is supplied to the gate terminal by the "off pulse" storage time and fall time may be observed by means of an oscilloscope connected across the current sensing 4225-1. Gate turn-off test time is the time interval between the 10 percent point on the leading edge of the gate current off-pulse and the 90 percent pointon the trailing edge on-state current waveform. Fall time is the time interval between the 90 percent and 10 percent points on the trailingedge of the on-state current waveform. Turn-off time is the sum of storage time and fall time. Typical waveforms are shown on 4225-2. Typical gate turn-off circuit 42251 of 2MIL-STD-750D3. Test description. A turn-off thyristor can be switched from the on-state to the off-state with a control signal of appropriate polarity tothe gate terminal. The delay and fall times of anode current during the turn off of the thyristor are affected by gate trigger pulse variationsand anode circuit conditions. This test method establishes a test circuit and provision for measuring of critical test current or gate source voltage rise time shall not exceed 10 percent of the storage time cycle should be chosen considering heating effects of switching power losses. Sufficient anode current offtime of at least 10 times the off pulse width must be allowed to ensure that the DUT remains turned off after theturn-off pulse inductance of the anode circuit should be minimized to prevent anode voltage overshoot on Summary. The following conditions shall be specified in the detail repetition cycle (percent on-time). temperature (case or ambient). network (show circuit). turn-off current (peak); or gate source voltage and gate source "on" pulse width and "off" pulse width, amplitude, and delay time from gate "on" 42252MIL-STD-750DMETHOD "ON" VOLTAGE1. Purpose. The purpose of this test is to measure the voltage in the forward direction across the device under the Test circuit. See figure : When specified, switch SW1 shall be used to provide pulses of short-dutycycle to minimize device heating. When pulsing techniques are used, othersuitable peak-reading techniques shall be used to measure the necessaryparameters, and the duty cycle and pulse width shall be 4226-1. Test circuit for forward "on" Procedure. The supply voltage is adjusted to obtain the specified value of forward current through the device with SW1 and SW2closed. SW2 shall be opened, and then the forward voltage is read when the forward current equals the specified value. When thespecified test current is greater than ampere, the voltage measuring probes shall be connected to the device inside of the currentcarrying connections. For axial lead devices, the voltage measuring probe(s) shall contact the lead(s) at a point .375 inch ( mm) from the case. For all other devices, the voltage shall be measured across the normal electrical connection Summary. The following conditions shall be specified in the detail current (see 3.). cycle and pulse width when pulse techniques are to be used (see above note).METHOD RATE OF VOLTAGE RISE1. Purpose. The purpose of this test is to determine if the device is capable of blocking a forward voltage which is increasing at anexponential rate starting from zero without switching "on" in the forward Test circuit. R2 is chosen to discharge C between cycles when SW is opened and R L is a protective resistor chosen to limit themaximum device current if the device turns "on" during the voltage rise. Switch SW should have a closure time (including bounce) of notmore than T and be closed a minimum of 5 4231-1. Test circuit for exponential rate of voltage 4231-2. Waveforms across the of 2MIL-STD-750D3. Procedure. The voltage VAA shall be adjusted to the specified value with switch SW open (see figure 4231-1). The resistor, R1,shall be adjusted to achieve the specified rate of voltage rise, dv/dt, across the DUT with the specified gate bias condition applied. Therate of voltage rise is defined as shown on figure 4231-2. Close SW and monitor VFB on the response detector. A device shall beconsidered a failure if VFB does not rise to and maintain a value greater than the minimum specified forward-blocking voltage during thefirst 5 T of each voltage pulse after switch SW is Summary. The following conditions shall be specified in the detail voltage, of voltage rise, dv/dt (see figure 4231-2). of C and of forward-blocking voltage, condition, gate-to-cathode, as applicable:A: Bias (specify VGG, gate-to-cathode polarity, equivalent bias circuit resistance, Re).B: Resistance return (specify value of R3).C: Short : Open SeriesElectrical characteristics tests for tunnel diodesMIL-STD-750DMETHOD 4301JUNCTION CAPACITANCE1. Purpose. The purpose of this test is to determine the small signal junction capacitance of the tunnel diode under the Test circuit. See figure 4301-1. Test circuit for junction Procedure. Since junction capacitance is a function of bias it is necessary to specify the forward bias at which C1 is to bedetermined. The true value of junction capacitance (at a given bias) is obtained by subtracting the capacitance of the diode package fromthe observed capacitance. Isolation of the dc power supply from the complex impedance bridge (see figure 4301-1) is effected by the R1,L1, C2 branch of the Summary. The following conditions shall be specified in the detail for the circuit elements R1, C1, C2, L1, and 43011/2MIL-STD-750DMETHOD CHARACTERISTICS OF TUNNEL DIODES1. Purpose. The purpose of this test is to measure the static characteristics (Vp, Vv, Ip, Iv, VFP, and Rd) of the tunnel diode underthe specified conditions:2. Test circuit. See figures 4306-1 and 4306-1. Test circuit for static characteristics of tunnel diodes (dc method).FIGURE 4306-2. Test circuit for static characteristics of tunnel diodes (ac method).METHOD of 2MIL-STD-750DFIGURE 4306-3. Typical tunnel diode forward the measurement of the static characteristics by point by point method the circuit of figure 4306-1 shall beused. Resistor, R2, is small to obtain low voltage and low impedance. Resistor R3 is a current measuringresistor. Resistor R1 is much larger than R2. To obtain a plot in the negative resistance region R1 shall be lessthan the magnitude of the incremental negative resistance of the tunnel the measurement of the static forward characteristics of the device by oscillographic means the circuit shownon figure 4306-2 shall be used. The magnitude of R1 shall be less than the magnitude of the incremental negativeresistance of the tunnel diode. Resistance R3 is a current measuring resistor and should be chosen to give asuitable CRO deflection. Since the negative resistance is represented by the inverse slope of the I-V curvebetween the peak and valley voltage points, its approximate value can be estimated from the curve. For a moreaccurate method for the measurement of the negative resistance see method Summary. The following conditions shall be specified in the detail R1, R2, and R3 (see a. and b.). frequency (see b.).METHOD 4316SERIES INDUCTANCE1. Purpose. The purpose of this test is to measure the value of the small signal series inductance under the specified Test circuit. See figure 4316-1. Test circuit for series Procedure. The device shall be reverse biased for the series inductance measurement. A sufficiently high frequency signal shallbe employed to emphasize the inductive reactance, but not high enough to allow any capacitive parasitics to short circuit the device, thusprecluding the determination of LS. A recommended frequency device is one approximately 25 percent of the self resonant frequency ofthe DUT. Isolation of the dc power supply from the complex impedance is accomplished by the choke, L1, in conjunction with C1, R1, C2, branch (see figure 4316-1).4. Summary. The following conditions shall be specified in the detail for circuit elements, R1, L1, C1, and bias at which LS is 43161/2MIL-STD-750DMETHOD 4321NEGATIVE RESISTANCE1. Purpose. The purpose of this test is to determine the magnitude of the negative resistance under the specified Test circuit. See figures 4321-1 and 4321-1. Test circuit for negative resistance, short-circuit stable 4321-2. Test circuit for negative resistance, open-circuit stable Procedure. The magnitude of R1 shall be less than the incremental negative resistance of the tunnel diode. Resistor R3 is acurrent limiting resistor and should be chosen to give a suitable CRO deflection. Diode D1 is a half wave Short-circuit stable method. Shunt the tunnel diode with a variable resistor R4 (see figure 4321-1). Vary R4 until the slope of thenegative resistance appears horizontal (zero slope) on the curve trace. The shunting resistance is now equal to the magnitude of thenegative resistance, Rd. (R4 = Rd.) Open-circuit stable method. In series with the tunnel diode connect a variable resistor R4 (see figure 4321-2). Vary R4 until theslope in the negative resistance appears vertical (infinite slope) on the curve trace. The series resistance R4 is now equal to themagnitude of the negative resistance (R4 = Rd).4. Summary. The following conditions shall be specified in the detail impedance sensing resistor, resistor, 43211/2MIL-STD-750DMETHOD 4326SERIES RESISTANCE1. Purpose. The purpose of this test is to determine the series resistance of the device under the specified Test circuit. See figure 4326-1. Test circuit for series Procedure. The measurement of the series resistance shall be accomplished for the device when biased in the reverse direction(see figure 4326-1). The linearity of the ohmic region shall be assured and the value of the power dissipation shall be such that no erroris introduced as a result of excessive diode heating. The slope of the linear portion of the reverse biased tunnel diode shall be sealedwithin a specified accuracy in the direct determination of the series resistance of the Summary. The following conditions shall be specified in the detail sensing resistor bias at which R3 is to be 43261/2MIL-STD-750DMETHOD 4331SWITCHING TIME1. Purpose. The purpose of this test is to measure the switching time of the tunnel diode under the specified Test circuit. See figure 4331-1. Test circuit for switching Procedure. A block diagram of the measuring circuit is shown in figure 4331-1. To perform the switching time measurement, it isnecessary that the maximum generator current be greater than the diode peak current and that changes in generator current duringmeasurement time be negligible compared to IP. The oscilloscope input probe impedance shall be such that the current absorbed by theprobe is at all times less than the peak current of the Summary. The following conditions shall be specified in the detail time of 43311/2MIL-STD-750D5000 ClassHigh reliability space application testsMIL-STD-750DMETHOD LOT ACCEPTANCE TESTING1. Purpose. This method establishes the requirement for the lot acceptance testing of discrete device wafer lots or wafers intended forJANS level Apparatus. The apparatus used shall be in accordance with the apparatus requirements of the methods specified in table 5001-Iconditions. Alternate apparatus may be used when approved by the qualifying Procedure. The performance of the wafer lot acceptance tests shall be in accordance with the conditions specified in table a lot fails a test under the sampling plan, as an alternative to rejecting the entire lot, the manufacturer may elect to test each wafer in thelot for that parameter(s). All wafers successfully passing the test(s) shall be considered the lot for the remainder of the tests. All waferssuccessfully passing the test(s) shall be considered the lot for the remainder of the tests. All wafers failing any test shall be removedfrom the lot. Data obtained from all tests shall be recorded. The sequence of the tests in 5001-1 does not have to be adhered to,however, the test must be performed at the point in the processing (if specified) required in the conditions column of 5001-1. W herelimits are based on tolerances about an "approved design nominal", the nominal shall be stated in the maintenance plan submitted forapproval to the qualifying or acquiring activity. W here table 5001-1 limits are based on tolerances about the "mean", the mean shall bedetermined initially on measurements from a minimum of five lots and the mean shall be stated in the maintenance plan submitted forapproval to the qualifying or acquiring activity. In no case shall the "design nominal" or "mean" exceed the absolute limits specified intable Summary. The following conditions shall be specified in the applicable detail or limits, if other than those in table test methods, procedures, or equipment other than those specified in table of 2TABLE 5001-I. Wafer lot acceptance tests. Tests Conditions 1/ Limits Sample plan1. Wafer thicknessMeasurement shall beperformed after the finallap or polish. Allreading shall berecorded. 2/Maximum deviation ofr2 mil from approveddesign nominal 6 milminimumTwo wafer per lot if anymeasurement exceedslimits or revert to test ofeach Metallization thicknessAll reading shall Conductor: 8 k minimum for singlelevel metal and for thetop level of multi-levelmetal; 5 k minimumfor lower levels, with amaximum deviation ofr20 percent from theapproved Barrier: Maximumdeviation of r30 percentfrom the approveddesign wafer (or monitor)per lot. Reject lot ifmeasurement exceedslimits or revert to test ofeach SEMMIL-STD-750, method2077MIL-STD-750, method2077MIL-STD-750, method2077. Lot Glassivation thicknessAll readings shall k minimum for SiO2and 2 k for Si3N4 withmaximum deviation ofr20 percent fromapproved wafer (or monitor)per lot. Reject lot if anymeasurement exceedslimits or revert to test ofeach Gold backing thickness(when applicable)All readings shall accordance withapproved designnominal thickness wafer (or monitor)per lot. Reject lot if anymeasurement exceedslimits or revert to test ofeach wafer. 1/The manufacturer shall have documented procedures for performing each required test. These procedures shall be made available to the qualifying activity or acquiring activity upon request 2/This test is not required when the finished wafer design thickness is greater than 10 5002CAPACITANCE-VOLTAGE MEASUREMENTS TO DETERMINE OXIDE QUALITY1. Purpose. The purpose of this test is to determine the quality of an oxide layer as indicated by capacitance-voltage measurements ofa metal-oxide semiconductor capacitor. The overall shape and position of the initial C/V curve can be interpreted in terms of the chargedensity, and to a certain extent charge type, at the oxide-semiconductor interface. By applying an appropriate bias while heating thesample to a moderate temperature ( , +200qC), the mobile ion contamination level of the sample oxide may be Apparatus/materials. Capacitance-voltage plotting system complete with heated/cooled stage and probe (Princeton AppliedResearch Model 410, MSI Electronics Model 868 or equivalent). A C/V plotter may be constructed from the following components (seefigure for equipment setup). Manual meter (Boonton 72B or equivalent). recorder (hp 7035B or equivalent). voltmeter (Systron Donner 7050 or equivalent). power supply, 0-100 stage (Thermochuck TP-36 or equivalent). in Automatic C/V plotter. (CSM-16 or equivalent).3. Suggested Sample sample is typically a silicon wafer on which has been grown the oxide to be measured, or wafers with knownclean oxide which is exposed to a furnace at temperature to measure the furnace cleanliness. An array of metaldots on the surface of the oxide provides the top electrodes of the metal-oxide-semiconductor capacitors. Themetal may either have been deposited through a shadow mask to form the dots, or it may have been depositeduniformly over the oxide surface and then etched into the dot pattern by photolithographic techniques. Cleanlinessof the metal deposition is paramount. Contamination introduced during metal deposition is as catastrophic to theoxide quality as is contamination introduced during oxide growth. The metal shall have been annealed, except incases where the method is being used to investigate the effectiveness of :This test may also be used to determine metal deposition system cleanliness when used with oxide samplesknown to be contamination minimum dot size should be such that the capacitance of the MOS capacitor is > 20 oxide thickness is typically 1,100 . Reduced sensitivity results from oxide thickness greater than 2,000 . backside of the sample shall have the oxide removed to expose the silicon. The backside may have metal,such as aluminum or gold deposited on 50021 of C/V plot (at room temperature). the wafer on the heated/cooled stage. Use vacuum to hold the wafer firmly in the capacitance meter as necessary, place the paper in X-Y plotter and set-up the voltage source for thedesired the capacitor dot to be measured and carefully lower the probe to contact the pen on the X-Y plotter and sweep the voltage over the desired range so a C/V trace for an N-typesubstrate or P-type substrate, similar to that shown on figure 5002-2 is : If an anomalous trace is obtained, it may be because the capacitor is leaking or shorted. In this case, another dotshould be Mobile ion the capacitor dot measured in the probe making good contact, apply a positive bias of 1010 v/cm to the capacitor dot. (For a 1,000 thickoxide, this is a 10-volt bias.) A different voltage is acceptable, if the manufacturer can demonstrate the sample to +300qC r5qC with the bias applied. Hold at this temperature for three minutes (different timesmay be acceptable if the manufacturer can demonstrate effectiveness). the bias still applied, cool the sample to room temperature (the heating and cooling cycle can be automaticallyprogrammed if the Thermochuck system is used).NOTE: Be certain that the probe does not lose contact with the capacitor dot during the heat/cool cycle. If it should, thetest is invalid and should be the pen on the X-Y plotter and sweep the voltage over the range necessary to obtain a C/V trace similar tothat obtained in The trace may be displaced on the voltage scale from the original trace, but should beparallel to the original trace. Label this trace as the (+) a negative bias of the same magnitude selected in to the capacitor dot and repeat steps the pen on the X-Y plotter and sweep the voltage over the range again. This trace may be displaced fromthe two previous traces and should be labeled as the (-) automatic system that performs equivalent functions may be substituted for steps and the )VFB (voltage difference between original trace and bias trace, taken at 90 percent capacitancelevel (see figure 5002-2)).METHOD the mobile ion contamination concentration, No, as follows: Where: 0 = Permittivity of free space ( x 10-12 coulomb volt-1 m-1).Kox = Dielectric constant of the oxide ( for silicon dioxide).q = The charge on an electron ( x 10-19 coulomb).tox = Oxide thickness (in meters).Example:'VFB (measured from C/V curves similar to those shown on figure 5002-2) = (measured on wafer prior to metal deposition) = 950 . = x 1015/meter2 = x 1011/cm2So, the mobile ion contamination-level is x 1011 mobile ions per square centimeter in more information concerning the oxide and the semiconductor substrate can be obtained frominterpretation of the C/V Calibration. The voltage scale calibration of the X-Y plotter should be checked against the DVM during set-up. Other instrumentsshould be calibrated at regular Accuracy. The voltage accuracy obtainable is volt and the 'VFB accuracy obtainable is volt. The practical lower limit ofdetectability of mobile ion contamination is on the order of 2 x 1011 Documentation. Record results in appropriate control :Whelon, , "Graphical Relation Between Surface Parameters of Silicon, to be Used in Connections with MOS CapacitanceMeasurements", Phillips Res. Apt., 620-630 (1965).METHOD 50023MIL-STD-750DFIGURE 5002-1. Diagram of equipment set-up for measuring relationship of metal-insulator-semiconductor 5002-2. C/V 50024MIL-STD-750DFIGURE 5002-3. Mobile ion density versus voltage shift (V ). FBMETHOD 50025/6MIL-STD-750DMETHOD 5010CLEAN ROOM AND WORKSTATIONAIRBORNE PARTICLE CLASSIFICATION AND MEASUREMENT1. Purpose. This test method provides a classification system for and means of measuring air cleanliness. It is intended to be used inconjunction with the environmental controls specified in Air cleanliness classes. There are three classes defined by this test method. Classifications are based upon particle count with amaximum allowable number of particles per unit volume micron or larger or microns and larger. Particle counts are to be takenduring normal work activity periods and at a location which will yield the particle count of the air as it approaches the work Class 100 ( ). Particle counts must not exceed a total of 100 particles per cubic foot ( particles per liter) of a size of or Class 1000 (35). Particle counts must not exceed a total of 1,000 particles per cubic foot (35 particles per liter) of a size of or larger of 7 particles per cubic foot ( particles per liter) of a size microns and Class 10,000 (350). Particle counts must not exceed a total of 10,000 particles per cubic foot (350 particles per liter) of a size micron or larger or 65 particles per cubic foot ( particles per liter) of a size of microns and Class 100,000 (3,500). Particle counts must not exceed a total of 100,000 particles per cubic foot (3,500 particles per liter) of asize of micron or larger or 700 particles per cubic foot (25 particles per liter) of a size of microns and Particle counting methods. For proof of meeting the requirements of the class of clean room or clean work station, one or more ofthe following particle counting methods shall be employed on the site of Particle sizes micron and larger. The equipment to be used must employ the light scattering measurement principle asspecified in ASTM Particle sizes micron and larger. A microscopic counting of particles collected on a membrane filter, through which a sampleof the air to be measured has been drawn, may be used in lieu of the light scattering measurement principle as specified in ASTM F25and Monitoring techniques. Appropriate equipment shall be selected and monitoring routines established to measure the air cleanlinesslevels under normal use Items to be specified. The referenced general specification shall specify the following class of the workstation or clean frequency of test. Unless otherwise specified, this frequency shall be, at a minimum, once per month per working locations within the clean environment to be 50101/2

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